 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| PIC32MX3XX/4XX Family Data Sheet 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers (c) 2009 Microchip Technology Inc. Preliminary DS61143F Note the following details of the code protection feature on Microchip devices: * * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." * * Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP, Omniscient Code Generation, PICC, PICC-18, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS61143F-page ii Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX High-Performance 80 MHz MIPS-Based 32-bit Flash Microcontroller 64/100-Pin General Purpose and USB High-Performance 32-bit RISC CPU: * MIPS32(R) M4KTM 32-bit Core with 5-Stage Pipeline * 80 MHz Maximum Frequency * 1.56 DMIPS/MHz (Dhrystone 2.1) Performance at 0 Wait State Flash Access * Single-Cycle Multiply and High-Performance Divide Unit * MIPS16eTM Mode for Up to 40% Smaller Code Size * Two Sets of 32 Core Register Files (32-bit) to Reduce Interrupt Latency * Prefetch Cache Module to Speed Execution from Flash Microcontroller Features: * Operating Voltage Range of 2.3V to 3.6V * 32K to 512K Flash Memory (plus an additional 12KB of Boot Flash) * 8K to 32K SRAM Memory * Pin-Compatible with Most PIC24/dsPIC(R) Devices * Multiple Power Management Modes * Multiple Interrupt Vectors with Individually Programmable Priority * Fail-Safe Clock Monitor Mode * Configurable Watchdog Timer with On-Chip Low-Power RC Oscillator for Reliable Operation * Separate PLLs for CPU and USB Clocks * Two I2CTM Modules * Two UART Modules with: - RS-232, RS-485 and LIN 1.2 support - IrDA(R) with On-Chip Hardware Encoder and Decoder * Parallel Master and Slave Port (PMP/PSP) with 8-bit and 16-bit Data and Up to 16 Address Lines * Hardware Real-Time Clock/Calendar (RTCC) * Five 16-bit Timers/Counters (two 16-bit pairs combine to create two 32-bit timers) * Five Capture Inputs * Five Compare/PWM Outputs * Five External Interrupt Pins * High-Speed I/O Pins Capable of Toggling at Up to 80 MHz * High-Current Sink/Source (18 mA/18 mA) on All I/O Pins * Configurable Open-Drain Output on Digital I/O Pins Debug Features: * Two Programming and Debugging Interfaces: - 2-Wire Interface with Unintrusive Access and Real-time Data Exchange with Application - 4-wire MIPS(R) Standard Enhanced JTAG interface * Unintrusive Hardware-Based Instruction Trace * IEEE Std 1149.2 Compatible (JTAG) Boundary Scan Peripheral Features: * Atomic SET, CLEAR and INVERT Operation on Select Peripheral Registers * Up to 4-Channel Hardware DMA with Automatic Data Size Detection * USB 2.0 Compliant Full Speed Device and On-The-Go (OTG) Controller * USB has a Dedicated DMA Channel * 10 MHz to 40 MHz Crystal Oscillator * Internal 8 MHz and 32 kHz Oscillators Analog Features: * Up to 16-Channel 10-bit Analog-to-Digital Converter: - 1000 ksps Conversion Rate - Conversion Available During Sleep, Idle * Two Analog Comparators * 5V Tolerant Input Pins (digital pins only) (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 1 PIC32MX3XX/4XX TABLE 1: PIC32MX GENERAL PURPOSE - FEATURES GENERAL PURPOSE Timers/Capture/Compare Program Memory (KB) Programmable DMA Channels Data Memory (KB) EUART/SPI/I2CTM 10-bit A/D (ch) Comparators Device PIC32MX320F032H PIC32MX320F064H PIC32MX320F128H PIC32MX340F128H PIC32MX340F256H PIC32MX340F512H PIC32MX320F128L PIC32MX340F128L PIC32MX360F256L PIC32MX360F512L Legend: Note 1: 2: PT = TQFP 64 64 64 64 64 64 100 100 100 100 40 80 80 80 80 80 80 80 80 80 32 + 12(1) 64 + 12(1) 128 + 12(1) 128 + 12(1) 256 + 12(1) 512 + 12(1) 128 + 12(1) 128 + 12(1) 256 + 12(1) 512 + 12(1) 8 16 16 32 32 32 16 32 32 32 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 0 0 0 4 4 4 0 4 4 4 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No Yes Yes 2/2/2 2/2/2 2/2/2 2/2/2 2/2/2 2/2/2 2/2/2 2/2/2 2/2/2 2/2/2 16 16 16 16 16 16 16 16 16 16 2 2 2 2 2 2 2 2 2 2 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes PT, MR PT, MR PT, MR PT, MR PT, MR PT, MR PT PT PT PT MR = QFN This device features 12 KB Boot Flash memory. See Legend for an explanation of the acronyms. See Section 29.0 "Packaging Information" for details. TABLE 2: PIC32MX USB - FEATURES USB Timers/Capture/Compare Program Memory (KB) Dedicated USB DMA Channels Programmable DMA Channels Data Memory (KB) EUART/SPI/I2CTM 10-bit A/D (ch) Comparators Device PIC32MX420F032H PIC32MX440F128H PIC32MX440F256H PIC32MX440F512H PIC32MX440F128L PIC32MX460F256L PIC32MX460F512L Legend: Note 1: 2: PT = TQFP 64 64 64 64 100 100 100 80 80 80 80 80 80 80 32 + 12(1) 128 + 12 512 + 12 (1) 8 32 32 32 32 32 32 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 0 4 4 4 4 4 4 2 2 2 2 2 2 2 Yes Yes Yes Yes Yes Yes Yes No No No No No 2/1/2 2/1/2 2/1/2 2/1/2 2/2/2 16 16 16 16 16 16 16 2 2 2 2 2 2 2 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes PT, MR PT, MR PT, MR PT, MR PT PT PT 256 + 12(1) (1) 128 + 12(1) 256 + 12(1) 512 + 12(1) Yes 2/2/2 Yes 2/2/2 MR = QFN This device features 12 KB Boot Flash memory. See Legend for an explanation of the acronyms. See Section 29.0 "Packaging Information" for details. DS61143F-page 2 Preliminary (c) 2009 Microchip Technology Inc. Packages(2) PMP/PSP VREG Trace JTAG Pins MHz Packages(2) PMP/PSP VREG Trace JTAG Pins MHz PIC32MX3XX/4XX PIN DIAGRAM: 64-PIN QFN - GENERAL PURPOSE 64-Pin QFN (General Purpose) = Pins are up to 5V tolerant PMD5/RE5 PMD6/RE6 PMD7/RE7 PMA5/SCK2/CN8/RG6 PMA4/SDI2/CN9/RG7 PMA3/SDO2/CN10/RG8 MCLR PMA2/SS2/CN11/RG9 VSS VDD C1IN+/AN5/CN7/RB5 C1IN-/AN4/CN6/RB4 C2IN+/AN3/CN5/RB3 C2IN-/AN2/SS1/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 PGED1/PMA6/AN0/VREF+/CVREF+/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0 RF1 RF0 ENVREG VCAP/VDDCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 PMWR/OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/RD0 IC4/PMCS1/PMA14/INT4/RD11 IC3/PMCS2/PMA15/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/RTCC/INT1/RD8 Vss OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD SCL1/RG2 SDA1/RG3 U1RTS/BCLK1/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 PIC32MX3XXH 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 AVDD AVSS U2CTS/C1OUT/AN8/RB8 PMA7/C2OUT/AN9/RB9 TMS/CVREFOUT/PMA13/AN10/RB10 TDO/PMA12/AN11/RB11 VSS VDD TCK/PMA11/AN12/RB12 TDI/PMA10/AN13/RB13 PMALH/PMA1/U2RTS/BCLK2/AN14/RB14 PMALL/PMA0/AN15/OCFB/CN12/RB15 PMA9/U2RX/SDA2/CN17/RF4 PMA8/U2TX/SCL2/CN18/RF5 Note: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 3 PIC32MX3XX/4XX PIN DIAGRAM: 64-PIN TQFP - GENERAL PURPOSE 64-Pin TQFP (General Purpose) = Pins are up to 5V tolerant PMD5/RE5 PMD6/RE6 PMD7/RE7 PMA5/SCK2/CN8/RG6 PMA4/SDI2/CN9/RG7 PMA3/SDO2/CN10/RG8 MCLR PMA2/SS2/CN11/RG9 VSS VDD C1IN+/AN5/CN7/RB5 C1IN-/AN4/CN6/RB4 C2IN+/AN3/CN5/RB3 C2IN-/AN2/SS1/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 PGED1/PMA6/AN0/VREF+/CVREF+/CN2/RB0 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0 RF1 RF0 ENVREG VCAP/VDDCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 PMWR/OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIC32MX3XXH 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/RD0 IC4/PMCS1/PMA14/INT4/RD11 IC3/PMCS2/PMA15/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/RTCC/INT1/RD8 Vss OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD SCL1/RG2 SDA1/RG3 U1RTS/BCLK1/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 AVDD AVSS U2CTS/C1OUT/AN8/RB8 PMA7/C2OUT/AN9/RB9 TMS/CVREFOUT/PMA13/AN10/RB10 TDO/PMA12/AN11/RB11 VSS VDD TCK/PMA11/AN12/RB12 TDI/PMA10/AN13/RB13 PMALH/PMA1/U2RTS/BCLK2/AN14/RB14 PMALL/PMA0/AN15/OCFB/CN12/RB15 PMA9/U2RX/SDA2/CN17/RF4 PMA8/U2TX/SCL2/CN18/RF5 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DS61143F-page 4 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX PIN DIAGRAM: 100-PIN TQFP - GENERAL PURPOSE 100-Pin TQFP (General Purpose) = Pins are up to 5V tolerant 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PMD4/RE4 PMD3/RE3 PMD2/RE2 TRD0/RG13 TRD1/RG12 TRD2/RG14 PMD1/RE1 PMD0/RE0 TRD3/RA7 TRCLK/RA6 PMD8/RG0 PMD9/RG1 PMD10/RF1 PMD11/RF0 ENVREG VCAP/VDDCORE PMD15/CN16/RD7 PMD14/CN15/RD6 PMRD/CN14/RD5 PMWR/OC5/CN13/RD4 PMD13/CN19/RD13 PMD12/IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1 RG15 VDD PMD5/RE5 PMD6/RE6 PMD7/RE7 T2CK/RC1 T3CK/RC2 T4CK/RC3 T5CK/RC4 PMA5/SCK2/CN8/RG6 PMA4/SDI2/CN9/RG7 PMA3/SDO2/CN10/RG8 MCLR PMA2/SS2/CN11/RG9 VSS VDD TMS/RA0 INT1/RE8 INT2/RE9 C1IN+/AN5/CN7/RB5 C1IN-/AN4/CN6/RB4 C2IN+/AN3/CN5/RB3 C2IN-/AN2/SS1/CN4/RB2 PGEC1/AN1/CN3/RB1 PGED1/AN0/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PIC32MX3XXL 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VSS SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/RD0 IC4/PMCS1/PMA14/RD11 IC3/PMCS2/PMA15/RD10 IC2/RD9 IC1/RTCC/RD8 INT4/RA15 INT3/RA14 VSS OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3 (c) 2009 Microchip Technology Inc. PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 PMA7/VREF-/CVREF-/RA9 PMA6/VREF+/CVREF+/RA10 AVDD AVSS C1OUT/AN8/RB8 C2OUT/AN9/RB9 CVREFOUT/PMA13/AN10/RB10 PMA12/AN11/RB11 VSS VDD TCK/RA1 U2RTS/BCLK2/RF13 U2CTS/RF12 PMA11/AN12/RB12 PMA10/AN13/RB13 PMALH/PMA1/AN14/RB14 PMALL/PMA0/AN15/OCFB/CN12/RB15 VSS VDD CN20/U1CTS/RD14 U1RTS/BCLK1/CN21/RD15 PMA9/U2RX/CN17/RF4 PMA8/U2TX/CN18/RF5 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Preliminary DS61143F-page 5 PIC32MX3XX/4XX PIN DIAGRAM: 64-PIN QFN - USB 64-Pin QFN (USB) = Pins are up to 5V tolerant 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PMD5/RE5 PMD6/RE6 PMD7/RE7 PMA5/SCK2/CN8/RG6 PMA4/SDI2/CN9/RG7 PMA3/SDO2/CN10/RG8 MCLR PMA2/SS2/CN11/RG9 VSS VDD VBUSON/C1IN+/AN5/CN7/RB5 C1IN-/AN4/CN6/RB4 C2IN+/AN3/CN5/RB3 C2IN-/AN2/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 PGED1/EMUD1/PMA6/AN0/VREF+/CVREF+/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 RF1 RF0 ENVREG VCAP/VDDCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 PMWR/OC5/IC5/CN13/RD4 OC4/U1TX/RD3 OC3/U1RX/RD2 OC2/U1RTS/BCLK1/RD1 PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0 PIC32MX4XXH 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/INT0/RD0 IC4/PMCS1/PMA14/INT4/RD11 IC3/PMCS2/PMA15/INT3/SCL1/RD10 IC2/U1CTS//INT2/SDA1/RD9 IC1/RTCC/INT1/RD8 Vss OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD D+/RG2 D-/RG3 VUSB VBUS USBID/RF3 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 AVDD AVSS U2CTS/C1OUT/AN8/RB8 PMA7/C2OUT/AN9/RB9 TMS/CVREFOUT/PMA13/AN10/RB10 TDO/PMA12/AN11/RB11 VSS VDD TCK/PMA11/AN12/RB12 TDI/PMA10/AN13/RB13 PMALH/PMA1/U2RTS/BCLK2/AN14/RB14 PMALL/PMA0/AN15/OCFB/CN12/RB15 PMA9/U2RX/SDA2/CN17/RF4 PMA8/U2TX/SCL2/CN18/RF5 Note: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. DS61143F-page 6 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX PIN DIAGRAM: 64-PIN TQFP - USB 64-Pin TQFP (USB) = Pins are up to 5V tolerant PMD5/RE5 PMD6/RE6 PMD7/RE7 PMA5/SCK2/CN8/RG6 PMA4/SDI2/CN9/RG7 PMA3/SDO2/CN10/RG8 MCLR PMA2/SS2/CN11/RG9 VSS VDD VBUSON/C1IN+/AN5/CN7/RB5 C1IN-/AN4/CN6/RB4 C2IN+/AN3/CN5/RB3 C2IN-/AN2/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 PGED1/EMUD1/PMA6/AN0/VREF+/CVREF+/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0 RF1 RF0 ENVREG VCAP/VDDCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 PMWR/OC5/IC5/CN13/RD4 OC4/U1TX/RD3 OC3/U1RX/RD2 OC2/U1RTS/BCLK1/RD1 SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/INT0/RD0 IC4/PMCS1/PMA14/INT4/RD11 IC3/PMCS2/PMA15/INT3/SCL1/RD10 IC2/U1CTS//INT2/SDA1/RD9 IC1/RTCC/INT1/RD8 Vss OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD D+/RG2 D-/RG3 VUSB VBUS USBID/RF3 PIC32MX4XXH (c) 2009 Microchip Technology Inc. PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 AVDD AVSS U2CTS/C1OUT/AN8/RB8 PMA7/C2OUT/AN9/RB9 TMS/CVREFOUT/PMA13/AN10/RB10 TDO/PMA12/AN11/RB11 VSS VDD TCK/PMA11/AN12/RB12 TDI/PMA10/AN13/RB13 PMALH/PMA1/U2RTS/BCLK2/AN14/RB14 PMALL/PMA0/AN15/OCFB/CN12/RB15 PMA9/U2RX/SDA2/CN17/RF4 PMA8/U2TX/SCL2/CN18/RF5 Preliminary DS61143F-page 7 PIC32MX3XX/4XX PIN DIAGRAM: 100-PIN TQFP - USB 100-Pin TQFP (USB) = Pins are up to 5V tolerant RG15 VDD PMD5/RE5 PMD6/RE6 PMD7/RE7 T2CK/RC1 T3CK/RC2 T4CK/RC3 SDI1/T5CK/RC4 PMA5/SCK2/CN8/RG6 PMA4/SDI2/CN9/RG7 PMA3/SDO2/CN10/RG8 MCLR PMA2/SS2/CN11/RG9 VSS VDD TMS/RA0 INT1/RE8 INT2/RE9 VBUSON/C1IN+/AN5/CN7/RB5 C1IN-/AN4/CN6/RB4 C2IN+/AN3/CN5/RB3 C2IN-/AN2/CN4/RB2 PGEC1/AN1/CN3/RB1 PGED1/AN0/CN2/RB0 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PMD4/RE4 PMD3/RE3 PMD2/RE2 TRD0/RG13 TRD1/RG12 TRD2/RG14 PMD1/RE1 PMD0/RE0 TRD3/RA7 TRCLK/RA6 PMD8/RG0 PMD9/RG1 PMD10/RF1 PMD11/RF0 ENVREG VCAP/VDDCORE PMD15/CN16/RD7 PMD14/CN15/RD6 PMRD/CN14/RD5 PMWR/OC5/CN13/RD4 PMD13/CN19/RD13 PMD12/IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PIC32MX4XXL 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VSS SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 SDO1/OC1/INT0/RD0 IC4/PMCS1/PMA14/RD11 IC3/SCK1/PMCS2/PMA15/RD10 IC2/SS1/RD9 IC1/RTCC/RD8 SDA1/INT4/RA15 SCL1/INT3/RA14 VSS OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 D+/RG2 D-/RG3 VUSB VBUS U1TX/RF8 U1RX/RF2 USBID/RF3 PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 PMA7/VREF-/CVREF-/RA9 PMA6/VREF+/CVREF+/RA10 AVDD AVSS C1OUT/AN8/RB8 C2OUT/AN9/RB9 CVREFOUT/PMA13/AN10/RB10 PMA12/AN11/RB11 VSS VDD TCK/RA1 U2RTS/BCLK2/RF13 U2CTS/RF12 PMA11/AN12/RB12 PMA10/AN13/RB13 PMALH/PMA1/AN14/RB14 PMALL/PMA0/AN15/OCFB/CN12/RB15 VSS VDD CN20/U1CTS/RD14 U1RTS/BCLK1/CN21/RD15 PMA9/U2RX/CN17/RF4 PMA8/U2TX/CN18/RF5 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DS61143F-page 8 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX Table of Contents High-Performance 80 MHz MIPS-Based 32-bit Flash Microcontroller 64/100-Pin General Purpose and USB ..................................... 1 1.0 Device Overview ........................................................................................................................................................................ 11 2.0 Guidelines for Getting Started with 32-bit Microcontrollers ........................................................................................................ 15 3.0 PIC32MX MCU........................................................................................................................................................................... 19 4.0 Memory Organization ................................................................................................................................................................. 25 5.0 Flash Program Memory.............................................................................................................................................................. 55 6.0 Resets ........................................................................................................................................................................................ 57 7.0 Interrupt Controller ..................................................................................................................................................................... 59 8.0 Oscillator Configuration .............................................................................................................................................................. 63 9.0 Prefetch Cache........................................................................................................................................................................... 65 10.0 Direct Memory Access (DMA) Controller ................................................................................................................................... 67 11.0 USB On-The-Go (OTG).............................................................................................................................................................. 69 12.0 I/O Ports ..................................................................................................................................................................................... 71 13.0 Timer1 ........................................................................................................................................................................................ 73 14.0 Timers 2, 3, 4, 5 ......................................................................................................................................................................... 75 15.0 Input Capture.............................................................................................................................................................................. 77 16.0 Output Compare......................................................................................................................................................................... 79 17.0 Serial Peripheral Interface (SPI)................................................................................................................................................. 81 18.0 Inter-Integrated Circuit (I2CTM) ................................................................................................................................................... 83 19.0 Universal Asynchronous Receiver Transmitter (UART) ............................................................................................................. 85 20.0 Parallel Master Port (PMP)......................................................................................................................................................... 89 21.0 Real-Time Clock and Calendar (RTCC)..................................................................................................................................... 91 22.0 10-bit Analog-to-Digital Converter (ADC) ................................................................................................................................... 93 23.0 Comparator ................................................................................................................................................................................ 95 24.0 Comparator Voltage Reference (CVref) ..................................................................................................................................... 97 25.0 Power-Saving Features.............................................................................................................................................................. 99 26.0 Special Features ...................................................................................................................................................................... 101 27.0 Instruction Set .......................................................................................................................................................................... 113 28.0 Development Support............................................................................................................................................................... 121 28.0 Electrical Characteristics .......................................................................................................................................................... 119 29.0 Packaging Information.............................................................................................................................................................. 157 INDEX ................................................................................................................................................................................................ 167 Worldwide Sales and Service ............................................................................................................................................................ 170 (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 9 PIC32MX3XX/4XX TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS61143F-page 10 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX 1.0 Note: DEVICE OVERVIEW This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the appropriate section of the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32) This document contains device-specific information for the PIC32MX3XX/4XX devices. Figure 1-1 shows a general block diagram of the core and peripheral modules in the PIC32MX3XX/4XX families of devices. Table 1-1 lists the functions of the various pins shown in the pinout diagrams. FIGURE 1-1: BLOCK DIAGRAM(1,2) OSC2/CLKO OSC1/CLKI VDDCORE/VCAP OSC/SOSC Oscillators FRC/LPRC Oscillators PLL DIVIDERS PLL-USB Timing Generation Precision Band Gap Reference USBCLK SYSCLK PBCLK ENVREG Voltage Regulator Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset VDD, VSS MCLR Peripheral Bus Clocked by SYSCLK PORTA Priority Interrupt Controller USB EJTAG INT DMAC CN1-22 Timer1-5 PWM OC 1-5 32 Peripheral Bus Clocked by PBCLK ICD JTAG BSCAN PORTB PORTC MIPS 32(R) M4K(R) CPU Core IS 32 32 DS 32 32 Bus Matrix 32 32 32 32 32 IC 1-5 SPI 1,2 PORTD I2C 1,2 32 PORTE Prefetch Module Data RAM Peripheral Bridge PMP 10-bit ADC PORTF 128 UART 1,2 128-bit wide Program Flash Memory Flash Controller RTCC Comparators PORTG Note 1: 2: Some features are not available on all device variants. BOR functionality is provided when the on-board voltage regulator is enabled. (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 11 PIC32MX3XX/4XX TABLE 1-1: Pin Name AN0-AN15 CLKI CLKO OSC1 OSC2 SOSCI SOSCO CN0-CN21 IC1-IC5 OCFA OC1-OC5 OCFB INT0 INT1 INT2 INT3 INT4 RA0-RA15 RB0-RB15 RC0-RC15 RD0-RD15 RE0-RE15 RF0-RF15 RG0, RG1, RG4-RG15 RG2, RG3 T1CK T2CK T3CK T4CK T5CK U1CTS U1RTS U1RX U1TX U2CTS U2RTS U2RX U2TX PINOUT I/O DESCRIPTIONS Pin Type I I O I I/O I O I I I O I I I I I I I/O I/O I/O I/O I/O I/O I/O I I I I I I I O I O I O I O Buffer Type Analog Analog input channels. Description ST/CMOS External clock source input. Always associated with OSC1 pin function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator -- mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function. ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. -- Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. ST/CMOS 32.768 kHz low-power oscillator crystal input; CMOS otherwise. -- 32.768 kHz low-power oscillator crystal output. ST ST ST -- ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST -- ST -- ST -- ST -- Change notification inputs. Can be software programmed for internal weak pull-ups on all inputs. Capture inputs 1-5. Compare Fault A input. Compare outputs 1 through 5. Output Compare Fault B Input. External interrupt 0. External interrupt 1. External interrupt 2. External interrupt 3. External interrupt 4. PORTA is a bidirectional I/O port. PORTB is a bidirectional I/O port. PORTC is a bidirectional I/O port. PORTD is a bidirectional I/O port. PORTE is a bidirectional I/O port. PORTF is a bidirectional I/O port. PORTG is a bidirectional I/O port. PORTG input pins. Timer1 external clock input. Timer2 external clock input. Timer3 external clock input. Timer4 external clock input. Timer5 external clock input. UART1 clear to send. UART1 ready to send. UART1 receive. UART1 transmit. UART2 clear to send. UART2 ready to send. UART2 receive. UART2 transmit. Analog = Analog input O = Output P = Power I = Input Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer DS61143F-page 12 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX TABLE 1-1: Pin Name SCK1 SDI1 SDO1 SS1 SCK2 SDI2 SDO2 SS2 SCL1 SDA1 TMS TCK TDI TDO RTCC CVREF- CVREF+ CVREFOUT C1INC1IN+ C1OUT C2INC2IN+ C2OUT PMA0 PMA1 PMA2-PMPA15 PMENB PMCS1 PMCS2 PMD0-PMD15 PMRD PMWR PMALL PMALH PMRD/PMWR PMALL PMALH PMRD/PMWR PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Type I/O I O I/O I/O I O I/O I/O I/O I I I O O I I O I I O I I O I/O I/O O O O O I/O O O O O O O O O Buffer Type ST ST -- ST ST ST -- ST ST ST ST ST ST -- -- ANA ANA ANA ANA ANA -- ANA ANA -- TTL/ST TTL/ST -- -- -- -- TTL/ST -- -- -- -- -- -- -- -- Description Synchronous serial clock input/output for SPI1. SPI1 data in. SPI1 data out. SPI1 slave synchronization or frame pulse I/O. Synchronous serial clock input/output for SPI2. SPI2 data in. SPI2 data out. SPI2 slave synchronization or frame pulse I/O. Synchronous serial clock input/output for I2C1. Synchronous serial data input/output for I2C1. JTAG Test mode select pin. JTAG test clock input pin. JTAG test data input pin. JTAG test data output pin. Real-Time Clock Alarm Output. Comparator Voltage Reference (low). Comparator Voltage Reference (high). Comparator Voltage Reference Output. Comparator 1 Negative Input. Comparator 1 Positive Input. Comparator 1 Output. Comparator 2 Negative Input. Comparator 2 Positive Input. Comparator 2 Output. Parallel Master Port Address Bit 0 Input (Buffered Slave modes) and Output (Master modes). Parallel Master Port Address Bit 1 Input (Buffered Slave modes) and Output (Master modes). Parallel Master Port Address (Demultiplexed Master Modes). Parallel Master Port Enable Strobe (Master mode 1). Parallel Master Port Chip Select 1 Strobe. Parallel Master Port Chip Select 2 Strobe. Parallel Master Port Data (Demultiplexed Master mode) or Address/Data (Multiplexed Master modes). Parallel Master Port Read Strobe. Parallel Master Port Write Strobe. Parallel Master Port Address Latch Enable low-byte (Multiplexed Master modes). Parallel Master Port Address Latch Enable high-byte (Multiplexed Master modes). Parallel Master Port Read/Write Strobe (Master mode 1). Parallel Master Port Address Latch Enable low-byte (Multiplexed Master modes). Parallel Master Port Address Latch Enable high-byte (Multiplexed Master modes). Parallel Master Port Read/Write Strobe (Master mode 1). Analog = Analog input O = Output P = Power I = Input Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 13 PIC32MX3XX/4XX TABLE 1-1: Pin Name VBUS VUSB VBUSON D+ D- USBID ENVREG TRCLK TRD0-TRD3 PGED1 PGEC1 PGED2 PGEC2 MCLR AVdd AVss Vdd Vcap/Vddcore Vss VREF+ VREF- PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Type I P O I/O I/O I I O O I/O I I/O I I/P P P P P P I I Buffer Type ANA -- -- ANA ANA ST ST -- -- ST ST ST ST ST P P -- -- -- Analog Analog Description USB Bus Power Monitor. USB Internal Transceiver Supply. USB Host and OTG Bus Power Control Output. USB D+. USB D-. USB OTG ID Detect. Enable for On-Chip Voltage Regulator. Trace Clock. Trace Data Bits 0-3 Data I/O pin for programming/debugging communication channel 1. Clock input pin for programming/debugging communication channel 1. Data I/O pin for programming/debugging communication channel 2. Clock input pin for programming/debugging communication channel 2. Master Clear (Reset) input. This pin is an active-low Reset to the device. Positive supply for analog modules. This pin must be connected at all times. Ground reference for analog modules. Positive supply for peripheral logic and I/O pins. CPU logic filter capacitor connection. Ground reference for logic and I/O pins. Analog voltage reference (high) input. Analog voltage reference (low) input. Analog = Analog input O = Output P = Power I = Input Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer DS61143F-page 14 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX 2.0 GUIDELINES FOR GETTING STARTED WITH 32-BIT MICROCONTROLLERS This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" for a detailed description of the PIC32MX MCU. The manual is available from the Microchip web site (www.Microchip.com/PIC32). 2.2 Decoupling Capacitors Note: The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD, and AVSS is required. See Figure 2-1. Consider the following criteria when using decoupling capacitors: * Value and type of capacitor: Recommendation of 0.1 F (100 nF), 10-20V. This capacitor should be a low-ESR and have resonance frequency in the range of 20 MHz and higher. It is recommended that ceramic capacitors be used. * Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is within onequarter inch (6 mm) in length. * Handling high frequency noise: If the board is experiencing high frequency noise, upward of tens of MHz, add a second ceramic-type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 F to 0.001 F. Place this second capacitor next to the primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible. For example, 0.1 F in parallel with 0.001 F. * Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum thereby reducing PCB track inductance. 2.1 Basic Connection Requirements Getting started with the PIC32MX3XX/4XX family of 32-bit Microcontrollers (MCU) requires attention to a minimal set of device pin connections before proceeding with development. The following is a list of pin names, which must always be connected: * All VDD and VSS pins (see Section 2.2) * All AVDD and AVSS pins (regardless if ADC module is not used) (see Section 2.2) * VCAP/VDDCORE (see Section 2.3) * MCLR pin (see Section 2.4) * PGECx/PGEDx pins used for In-Circuit Serial ProgrammingTM (ICSPTM) and debugging purposes (see Section 2.5) * OSC1 and OSC2 pins when external oscillator source is used (see Section 2.8) Additionally, the following pins may be required: * VREF+/VREF- pins used when external voltage reference for ADC module is implemented Note: The AVDD and AVSS pins must be connected independent of ADC use and ADC voltage reference source. (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 15 PIC32MX3XX/4XX FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION 0.1 F Ceramic CBP VDD VCAP/VDDCORE VSS 2.4 Master Clear (MCLR) Pin The MCLR pin provides for two specific device functions: * Device Reset * Device Programming and Debugging Pulling The MCLR pin low generates a device reset. Figure 2-2 shows a typical MCLR circuit. During device programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R and C will need to be adjusted based on the application and PCB requirements. For example, as shown in Figure 2-2, it is recommended that the capacitor C, be isolated from the MCLR pin during programming and debugging operations. Place the components shown in Figure 2-2 within one-quarter inch (6 mm) from the MCLR pin. VDD R R1 MCLR C PIC32MX VSS VDD VDD VSS 0.1 F Ceramic CBP 0.1 F Ceramic CBP AVDD AVSS VDD 0.1 F Ceramic CBP VSS 0.1 F Ceramic CBP 10 2.2.1 BULK CAPACITORS The use of a bulk capacitor is recommended to improve power supply stability. Typical values range from 4.7 F to 47 F. This capacitor should be located as close to the device as possible. FIGURE 2-2: EXAMPLE OF MCLR PIN CONNECTIONS VDD R R1 JP C MCLR PIC32MX 2.3 2.3.1 Capacitor on Internal Voltage Regulator (VCAP/VDDCORE) INTERNAL REGULATOR MODE A low-ESR (< 5 Ohms) capacitor is required on the VCAP/VDDCORE pin, which is used to stabilize the internal voltage regulator output. The VCAP/VDDCORE pin must not be connected to VDD, and must have a 10 F capacitor, with at least a 6V rating, connected to ground. The type can be ceramic or tantalum. Refer to Section 28.0 "Electrical Characteristics" for additional information. This mode is enabled by connecting the ENVREG pin to VDD. Note 1: R 10 k is recommended. A suggested starting value is 10 k. Ensure that the MCLR pin VIH and VIL specifications are met. R1 470 will limit any current flowing into MCLR from the external capacitor C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met. The capacitor can be sized to prevent unintentional resets from brief glitches or to extend the device reset period during POR. 2: 2.3.2 EXTERNAL REGULATOR MODE 3: In this mode the core voltage is supplied externally through the VDDCORE pin. A low-ESR capacitor of 10 F is recommended on the VDDCORE pin. This mode is enabled by grounding the ENVREG pin. The placement of this capacitor should be close to the VCAP/VDDCORE. It is recommended that the trace length not exceed one-quarter inch (6 mm). Refer to Section 26.3 "On-Chip Voltage Regulator" for details. DS61143F-page 16 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX 2.5 ICSP Pins The PGECx and PGEDx pins are used for In-Circuit Serial ProgrammingTM (ICSPTM) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms. Pull-up resistors, series diodes, and capacitors on the PGECx and PGEDx pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternately, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high (VIH) and input low (VIL) requirements. Ensure that the "Communication Channel Select" (i.e., PGECx/PGEDx pins) programmed into the device matches the physical connections for the ICSP to MPLAB(R) ICD 2, MPLAB(R) ICD 3, or MPLAB(R) REAL ICETM. For more information on ICD 2, ICD 3, and REAL ICE connection requirements, refer to the following documents that are available on the Microchip website. * "MPLAB(R) ICD 2 In-Circuit Debugger User's Guide" DS51331 * "Using MPLAB(R) ICD 2" (poster) DS51265 * "MPLAB(R) ICD 2 Design Advisory" DS51566 * "Using MPLAB(R) ICD 3" (poster) DS51765 * "MPLAB(R) ICD 3 Design Advisory" DS51764 * "MPLAB(R) REAL ICETM In-Circuit Debugger User's Guide" DS51616 * "Using MPLAB(R) REAL ICETM" (poster) DS51749 Pull-up resistors, series diodes, and capacitors on the TMS, TDO, TDI, and TCK pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternately, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high (VIH) and input low (VIL) requirements. 2.7 Trace The trace pins can be connected to a hardware-traceenabled programmer to provide a compress real time instruction trace. When used for trace the TRD3, TRD2, TRD1, TRD0, and TRCLK pins should be dedicated for this use. The trace hardware requires a 22 Ohm series resistor between the trace pins and the trace connector. 2.8 External Oscillator Pins Many MCUs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 8.0 "Oscillator Configuration" for details). The oscillator circuit should be placed on the same side of the board as the device. Also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12 mm) distance between them. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate them from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. A suggested layout is shown in Figure 2-3. 2.6 JTAG The TMS, TDO, TDI, and TCK pins are used for testing and debugging according to the Joint Test Action Group (JTAG) standard. It is recommended to keep the trace length between the JTAG connector and the JTAG pins on the device as short as possible. If the JTAG connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms. FIGURE 2-3: SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT Oscillator Secondary Guard Trace Guard Ring Main Oscillator (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 17 PIC32MX3XX/4XX 2.9 Configuration of Analog and Digital Pins During ICSP Operations 2.10 Unused I/Os Unused I/O pins should not be allowed to float as inputs. They can be configured as outputs and driven to a logic-low state. Alternately, inputs can be reserved by connecting the pin to VSS through a 1k to 10k resistor and configuring the pin as an input. If MPLAB ICD 2, ICD 3, or REAL ICE is selected as a debugger, it automatically initializes all of the A/D input pins (ANx) as "digital" pins by setting all bits in the ADPCFG register. The bits in this register that correspond to the A/D pins that are initialized by MPLAB ICD 2, ICD 3, or REAL ICE, must not be cleared by the user application firmware; otherwise, communication errors will result between the debugger and the device. If your application needs to use certain A/D pins as analog input pins during the debug session, the user application must clear the corresponding bits in the ADPCFG register during initialization of the ADC module. When MPLAB ICD 2, ICD 3, or REAL ICE is used as a programmer, the user application firmware must correctly configure the ADPCFG register. Automatic initialization of this register is only done during debugger operation. Failure to correctly configure the register(s) will result in all A/D pins being recognized as analog input pins, resulting in the port value being read as a logic '0', which may affect user application functionality. DS61143F-page 18 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX 3.0 Note: PIC32MX MCU This data sheet summarizes the features of the PIC32MX3XX/4XX Family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" Section 2. "MCU" (DS61113) for a detailed description of the PIC32MX MCU. The manual is available from the Microchip web site (www.Microchip.com/PIC32). Resources for the MIPS32(R) M4K(R) Processor Core are available at www.mips.com/products/cores/32-bit-cores/ mips32-m4k/#. The MCU module is the heart of the PIC32MX3XX/4XX Family processor. The MCU fetches instructions, decodes each instruction, fetches source operands, executes each instruction, and writes the results of instruction execution to the proper destinations. 3.1 Features * 5-stage pipeline * 32-bit Address and Data Paths * MIPS32 Enhanced Architecture (Release 2) - Multiply-Accumulate and Multiply-Subtract Instructions - Targeted Multiply Instruction - Zero/One Detect Instructions - WAIT Instruction - Conditional Move Instructions (MOVN, MOVZ) - Vectored interrupts - Programmable exception vector base - Atomic interrupt enable/disable - GPR shadow registers to minimize latency for interrupt handlers - Bit field manipulation instructions * MIPS16eTM Code Compression - 16-bit encoding of 32-bit instructions to improve code density - Special PC-relative instructions for efficient loading of addresses and constants - SAVE & RESTORE macro instructions for setting up and tearing down stack frames within subroutines - Improved support for handling 8 and 16-bit data types * Simple Fixed Mapping Translation (FMT) mechanism * Simple Dual Bus Interface - Independent 32-bit address and data busses - Transactions can be aborted to improve interrupt latency * Autonomous Multiply/Divide Unit - Maximum issue rate of one 32x16 multiply per clock - Maximum issue rate of one 32x32 multiply every other clock - Early-in iterative divide. Minimum 11 and maximum 34 clock latency (dividend (rs) sign extension-dependent) * Power Control - Minimum frequency: 0 MHz - Low-Power mode (triggered by WAIT instruction) - Extensive use of local gated clocks * EJTAG Debug and Instruction Trace - Support for single stepping - Virtual instruction and data address/value - breakpoints - PC tracing with trace compression FIGURE 3-1: MCU BLOCK DIAGRAM EJTAG MDU Trace TAP Trace I/F Off-Chip Debug I/F FMT Bus Interface Dual Bus I/F System Coprocessor Power Mgmt (c) 2009 Microchip Technology Inc. Preliminary Bus Matrix DS61143F-page 19 Execution Core (RF/ALU/Shift) PIC32MX3XX/4XX 3.2 Architecture Overview 3.2.2 MULTIPLY/DIVIDE UNIT (MDU) The PIC32MX3XX/4XX Family core contains several logic blocks working together in parallel, providing an efficient high performance computing engine. The following blocks are included with the core: * Execution Unit * Multiply/Divide Unit (MDU) * System Control Coprocessor (CP0) * Fixed Mapping Translation (FMT) * Dual Internal Bus interfaces * Power Management * MIPS16e Support * Enhanced JTAG (EJTAG) Controller The PIC32MX3XX/4XX Family core includes a multiply/divide unit (MDU) that contains a separate pipeline for multiply and divide operations. This pipeline operates in parallel with the integer unit (IU) pipeline and does not stall when the IU pipeline stalls. This allows MDU operations to be partially masked by system stalls and/or other integer unit instructions. The high-performance MDU consists of a 32x16 booth recoded multiplier, result/accumulation registers (HI and LO), a divide state machine, and the necessary multiplexers and control logic. The first number shown (`32' of 32x16) represents the rs operand. The second number (`16' of 32x16) represents the rt operand. The PIC32MX core only checks the value of the latter (rt) operand to determine how many times the operation must pass through the multiplier. The 16x16 and 32x16 operations pass through the multiplier once. A 32x32 operation passes through the multiplier twice. The MDU supports execution of one 16x16 or 32x16 multiply operation every clock cycle; 32x32 multiply operations can be issued every other clock cycle. Appropriate interlocks are implemented to stall the issuance of back-to-back 32x32 multiply operations. The multiply operand size is automatically determined by logic built into the MDU. Divide operations are implemented with a simple 1 bit per clock iterative algorithm. An early-in detection checks the sign extension of the dividend (rs) operand. If rs is 8 bits wide, 23 iterations are skipped. For a 16bit-wide rs, 15 iterations are skipped, and for a 24-bitwide rs, 7 iterations are skipped. Any attempt to issue a subsequent MDU instruction while a divide is still active causes an IU pipeline stall until the divide operation is completed. Table 3-1 lists the repeat rate (peak issue rate of cycles until the operation can be reissued) and latency (number of cycles until a result is available) for the PIC32MX core multiply and divide instructions. The approximate latency and repeat rates are listed in terms of pipeline clocks. 3.2.1 EXECUTION UNIT The PIC32MX3XX/4XX Family core execution unit implements a load/store architecture with single-cycle ALU operations (logical, shift, add, subtract) and an autonomous multiply/divide unit. The core contains thirty-two 32-bit general purpose registers used for integer operations and address calculation. One additional register file shadow set (containing thirty-two registers) is added to minimize context switching overhead during interrupt/exception processing. The register file consists of two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline. The execution unit includes: * 32-bit adder used for calculating the data address * Address unit for calculating the next instruction address * Logic for branch determination and branch target address calculation * Load aligner * Bypass multiplexers used to avoid stalls when executing instructions streams where data producing instructions are followed closely by consumers of their results * Leading Zero/One detect unit for implementing the CLZ and CLO instructions * Arithmetic Logic Unit (ALU) for performing bitwise logical operations * Shifter and Store Aligner DS61143F-page 20 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX TABLE 3-1: PIC32MX3XX/4XX FAMILY CORE HIGH-PERFORMANCE INTEGER MULTIPLY/DIVIDE UNIT LATENCIES AND REPEAT RATES Opcode MULT/MULTU, MADD/MADDU, MSUB/MSUBU MUL DIV/DIVU Operand Size (mul rt) (div rs) 16 bits 32 bits 16 bits 32 bits 8 bits 16 bits 24 bits 32 bits The MIPS architecture defines that the result of a multiply or divide operation be placed in the HI and LO registers. Using the Move-From-HI (MFHI) and MoveFrom-LO (MFLO) instructions, these values can be transferred to the general purpose register file. In addition to the HI/LO targeted operations, the MIPS32 architecture also defines a multiply instruction, MUL, which places the least significant results in the primary register file instead of the HI/LO register pair. By avoiding the explicit MFLO instruction, required when using the LO register, and by supporting multiple destination registers, the throughput of multiply-intensive operations is increased. Two other instructions, multiply-add (MADD) and multiply-subtract (MSUB), are used to perform the multiplyaccumulate and multiply-subtract operations. The MADD instruction multiplies two numbers and then adds Latency 1 2 2 3 12 19 26 33 Repeat Rate 1 2 1 2 11 18 25 32 the product to the current contents of the HI and LO registers. Similarly, the MSUB instruction multiplies two operands and then subtracts the product from the HI and LO registers. The MADD and MSUB operations are commonly used in DSP algorithms. 3.2.3 SYSTEM CONTROL COPROCESSOR (CP0) In the MIPS architecture, CP0 is responsible for the virtual-to-physical address translation, the exception control system, the processor's diagnostics capability, the operating modes (kernel, user, and debug), and whether interrupts are enabled or disabled. Configuration information, such as presence of options like MIPS16e, is also available by accessing the CP0 registers, listed in Table 3-2. TABLE 3-2: COPROCESSOR 0 REGISTERS Function Reserved in the PIC32MX3XX/4XX Family core Enables access via the RDHWR instruction to selected hardware registers Reports the address for the most recent address-related exception Processor cycle count Reserved in the PIC32MX3XX/4XX Family core Timer interrupt control Processor status and control Interrupt system status and control Shadow register set status and control Provides mapping from vectored interrupt to a shadow set Cause of last general exception Program counter at last exception Processor identification and revision Exception vector base register Configuration register Configuration register 1 Configuration register 2 Configuration register 3 Register Register Number Name 0-6 7 8 9 10 11 12 12 12 12 13 14 15 15 16 16 16 16 Reserved HWREna BadVAddr(1) Count(1) Reserved Compare(1) Status(1) IntCtl(1) SRSCtl(1) SRSMap(1) Cause(1) EPC(1) PRId EBASE Config Config1 Config2 Config3 (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 21 PIC32MX3XX/4XX TABLE 3-2: COPROCESSOR 0 REGISTERS (CONTINUED) Function Reserved in the PIC32MX3XX/4XX Family core Debug control and exception status Program counter at last debug exception Reserved in the PIC32MX3XX/4XX Family core Program counter at last error Debug handler scratchpad register Register Register Number Name 17-22 23 24 25-29 30 31 Note 1: 2: Reserved Debug(2) DEPC(2) Reserved ErrorEPC(1) DESAVE(2) Registers used in exception processing. Registers used during debug. Coprocessor 0 also contains the logic for identifying and managing exceptions. Exceptions can be caused by a variety of sources, including alignment errors in data, external events, or program errors. Table 3-3 shows the exception types in order of priority. TABLE 3-3: Exception Reset DSS DINT NMI Interrupt DIB AdEL IBE DBp Sys Bp RI CpU CEU Ov Tr DDBL / DDBS AdEL AdES DBE DDBL PIC32MX3XX/4XX FAMILY CORE EXCEPTION TYPES Description Assertion MCLR or a Power-On Reset (POR) EJTAG Debug Single Step EJTAG Debug Interrupt. Caused by the assertion of the external EJ_DINT input, or by setting the EjtagBrk bit in the ECR register Assertion of NMI signal Assertion of unmasked hardware or software interrupt signal EJTAG debug hardware instruction break matched Fetch address alignment error Fetch reference to protected address Instruction fetch bus error EJTAG Breakpoint (execution of SDBBP instruction) Execution of SYSCALL instruction Execution of BREAK instruction Execution of a Reserved Instruction Execution of a coprocessor instruction for a coprocessor that is not enabled Execution of a CorExtend instruction when CorExtend is not enabled Execution of an arithmetic instruction that overflowed Execution of a trap (when trap condition is true) EJTAG Data Address Break (address only) or EJTAG Data Value Break on Store (address + value) Load address alignment error Load reference to protected address Store address alignment error Store to protected address Load or store bus error EJTAG data hardware breakpoint matched in load data compare DS61143F-page 22 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX 3.3 Power Management 3.4 EJTAG Debug Support The PIC32MX3XX/4XX Family core offers a number of power management features, including low-power design, active power management, and power-down modes of operation. The core is a static design that supports slowing or halting the clocks, which reduces system power consumption during idle periods. The PIC32MX3XX/4XX Family core provides for an Enhanced JTAG (EJTAG) interface for use in the software debug of application and kernel code. In addition to standard user mode and kernel modes of operation, the PIC32MX3XX/4XX Family core provides a Debug mode that is entered after a debug exception (derived from a hardware breakpoint, single-step exception, etc.) is taken and continues until a debug exception return (DERET) instruction is executed. During this time, the processor executes the debug exception handler routine. The EJTAG interface operates through the Test Access Port (TAP), a serial communication port used for transferring test data in and out of the PIC32MX3XX/4XX Family core. In addition to the standard JTAG instructions, special instructions defined in the EJTAG specification define what registers are selected and how they are used. 3.3.1 INSTRUCTION-CONTROLLED POWER MANAGEMENT The mechanism for invoking power-down mode is through execution of the WAIT instruction. For more information on power management, see Section 25.0 "Power-Saving Features". 3.3.2 LOCAL CLOCK GATING The majority of the power consumed by the PIC32MX3XX/4XX Family core is in the clock tree and clocking registers. The PIC32MX family uses extensive use of local gated-clocks to reduce this dynamic power consumption. (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 23 PIC32MX3XX/4XX NOTES: DS61143F-page 24 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX 4.0 Note: MEMORY ORGANIZATION This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" Section 3. "Memory Organization" (DS61115) for a detailed description of this peripheral. The manual is available from the Microchip web site (www.Microchip.com/PIC32). 4.1 PIC32MX3XX/4XX Memory Layout PIC32MX3XX/4XX microcontrollers implement two address spaces: Virtual and Physical. All hardware resources such as program memory, data memory, and peripherals are located at their respective physical addresses. Virtual addresses are exclusively used by the CPU to fetch and execute instructions as well as access peripherals. Physical addresses are used by peripherals such as DMA and Flash controller that access memory independently of CPU. PIC32MX3XX/4XX microcontrollers provide 4 GB of unified virtual memory address space. All memory regions including program, data memory, SFRs, and Configuration registers reside in this address space at their respective unique addresses. The program and data memories can be optionally partitioned into user and kernel memories. In addition, the data memory can be made executable, allowing PIC32MX3XX/4XX to execute from data memory. Key Features: * * * * * * * * 32-bit native data width Separate User and Kernel mode address space Flexible program Flash memory partitioning Flexible data RAM partitioning for data and program space Separate boot Flash memory for protected code Robust bus exception handling to intercept runaway code. Simple memory mapping with Fixed Mapping Translation (FMT) unit Cacheable and non-cacheable address regions (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 25 PIC32MX3XX/4XX FIGURE 4-1: MEMORY MAP ON RESET FOR PIC32MX320F032H, PIC32MX420F032H DEVICES(1) Virtual Memory Map 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 0xBF8FFFFF 0xBF800000 0xBD008000 0xBD007FFF Program Flash(2) 0xBD000000 0xA0002000 0xA0001FFF RAM(2) 0xA0000000 0x9FC02FF0 0x9FC02FFF 0x9FC02FEF 0x9FC02FEF Boot Flash 0x9FC00000 Reserved 0x9D008000 0x9D007FFF Program Flash(2) 0x9D000000 0x80002000 0x80001FFF RAM(2) 0x80000000 0x00000000 Note 1: 2: Reserved Reserved RAM(2) Reserved Program Flash(2) 0x1D000000 0x00002000 0x00001FFF 0x00000000 Reserved Reserved Device Configuration Registers Device Configuration Registers Boot Flash 0x1FC00000 0x1F900000 0x1F8FFFFF KSEG0 SFRs 0x1F800000 Reserved 0x1D008000 0x1D007FFF 0x1FC03000 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF Reserved Reserved KSEG1 SFRs Reserved Reserved Reserved Device Configuration Registers Physical Memory Map 0xFFFFFFFF Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. "Memory Organization" (DS61115)) and can be changed by initialization code provided by end-user development tools (refer to the specific development tool documentation for information). DS61143F-page 26 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX FIGURE 4-2: MEMORY MAP ON RESET FOR PIC32MX320F064H DEVICES(1) Virtual Memory Map 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 0xBF8FFFFF 0xBF800000 0xBD010000 0xBD00FFFF Program Flash(2) 0xBD000000 0xA0004000 0xA0003FFF RAM(2) 0xA0000000 0x9FC02FF0 0x9FC02FFF 0x9FC02FEF 0x9FC02FEF Boot Flash 0x9FC00000 Reserved 0x9D010000 0x9D00FFFF Program Flash(2) 0x9D000000 0x80004000 0x80003FFF RAM(2) 0x80000000 0x00000000 Note 1: 2: Reserved Reserved RAM (2) Physical Memory Map 0xFFFFFFFF Reserved Device Configuration Registers Reserved Reserved Reserved KSEG1 SFRs Reserved 0x1FC03000 Reserved Device Configuration Registers Device Configuration Registers Boot Flash 0x1FC00000 Reserved 0x1F900000 0x1F8FFFFF KSEG0 SFRs 0x1F800000 Reserved 0x1D010000 Reserved 0x1D00FFFF Program Flash(2) 0x1D000000 0x00004000 0x00003FFF 0x00000000 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. "Memory Organization" (DS61115)) and can be changed by initialization code provided by end-user development tools (refer to the specific development tool documentation for information). (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 27 PIC32MX3XX/4XX FIGURE 4-3: MEMORY MAP ON RESET FOR PIC32MX320F128H, PIC32MX320F128L DEVICES(1) Virtual Memory Map 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 0xBF8FFFFF 0xBF800000 0xBD020000 0xBD01FFFF Program Flash(2) 0xBD000000 0xA0004000 0xA0003FFF RAM(2) 0xA0000000 0x9FC02FF0 0x9FC02FFF 0x9FC02FEF 0x9FC02FEF Boot Flash 0x9FC00000 Reserved 0x9D020000 0x9D01FFFF Program Flash(2) 0x9D000000 0x80004000 0x80003FFF RAM(2) 0x80000000 0x00000000 Note 1: 2: Reserved Reserved RAM(2) Reserved Program Flash(2) 0x1D000000 0x00004000 0x00003FFF 0x00000000 Reserved Reserved Device Configuration Registers Device Configuration Registers Boot Flash 0x1FC00000 0x1F900000 0x1F8FFFFF KSEG0 SFRs 0x1F800000 Reserved 0x1D020000 0x1D01FFFF 0x1FC03000 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF Reserved Reserved KSEG1 SFRs Reserved Reserved Reserved Device Configuration Registers Physical Memory Map 0xFFFFFFFF Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. "Memory Organization" (DS61115)) and can be changed by initialization code provided by end-user development tools (refer to the specific development tool documentation for information). DS61143F-page 28 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX FIGURE 4-4: MEMORY MAP ON RESET FOR PIC32MX340F128H, PIC32MX340F128L, PIC32MX440F128H, PIC32MX440F128L DEVICES(1) Virtual Memory Map 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 0xBF8FFFFF 0xBF800000 0xBD020000 0xBD01FFFF Program Flash(2) 0xBD000000 0xA0008000 0xA0007FFF RAM(2) 0xA0000000 0x9FC02FF0 0x9FC02FFF 0x9FC02FEF 0x9FC02FEF Boot Flash 0x9FC00000 Reserved 0x9D020000 0x9D01FFFF Program Flash(2) 0x9D000000 0x80008000 0x80007FFF RAM(2) 0x80000000 0x00000000 Note 1: 2: Reserved Reserved RAM(2) Reserved Program Flash(2) 0x1D000000 0x00008000 0x00007FFF 0x00000000 Reserved Reserved Device Configuration Registers Device Configuration Registers Boot Flash 0x1FC00000 0x1F900000 0x1F8FFFFF KSEG0 SFRs 0x1F800000 Reserved 0x1D020000 0x1D01FFFF 0x1FC03000 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF Reserved Reserved KSEG1 SFRs Reserved Reserved Reserved Device Configuration Registers Physical Memory Map 0xFFFFFFFF Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. "Memory Organization" (DS61115)) and can be changed by initialization code provided by end-user development tools (refer to the specific development tool documentation for information). (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 29 PIC32MX3XX/4XX FIGURE 4-5: MEMORY MAP ON RESET FOR PIC32MX340F256H, PIC32MX360F256L, PIC32MX440F256H, PIC32MX460F256L DEVICES(1) Virtual Memory Map 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 0xBF8FFFFF 0xBF800000 0xBD040000 0xBD03FFFF Program Flash(2) 0xBD000000 0xA0008000 0xA0007FFF RAM(2) 0xA0000000 0x9FC02FF0 0x9FC02FFF 0x9FC02FEF 0x9FC02FEF Boot Flash 0x9FC00000 Reserved 0x9D040000 0x9D03FFFF Program Flash(2) 0x9D000000 0x80008000 0x80007FFF RAM(2) 0x80000000 0x00000000 Note 1: 2: Reserved Reserved RAM(2) Reserved Program Flash(2) 0x1D000000 0x00008000 0x00007FFF 0x00000000 Reserved Reserved Device Configuration Registers Device Configuration Registers Boot Flash 0x1FC00000 0x1F900000 0x1F8FFFFF KSEG0 SFRs 0x1F800000 Reserved 0x1D040000 0x1D03FFFF 0x1FC03000 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF Reserved Reserved KSEG1 SFRs Reserved Reserved Reserved Device Configuration Registers Physical Memory Map 0xFFFFFFFF Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. "Memory Organization" (DS61115)) and can be changed by initialization code provided by end-user development tools (refer to the specific development tool documentation for information). DS61143F-page 30 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX FIGURE 4-6: MEMORY MAP ON RESET FOR PIC32MX340F512H, PIC32MX360F512L, PIC32MX440F512H, PIC32MX460F512L DEVICES(1) Virtual Memory Map 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 0xBF8FFFFF 0xBF800000 0xBD080000 0xBD07FFFF Program Flash(2) 0xBD000000 0xA0008000 0xA0007FFF RAM(2) 0xA0000000 0x9FC02FF0 0x9FC02FFF 0x9FC02FEF 0x9FC02FEF Boot Flash 0x9FC00000 Reserved 0x9D080000 0x9D07FFFF Program Flash(2) 0x9D000000 0x80008000 0x80007FFF RAM(2) 0x80000000 0x00000000 Note 1: 2: Reserved Reserved RAM(2) Reserved Program Flash(2) 0x1D000000 0x00008000 0x00007FFF 0x00000000 Reserved Reserved Device Configuration Registers Device Configuration Registers Boot Flash 0x1FC00000 0x1F900000 0x1F8FFFFF KSEG0 SFRs 0x1F800000 Reserved 0x1D080000 0x1D07FFFF 0x1FC03000 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF Reserved Reserved KSEG1 SFRs Reserved Reserved Reserved Device Configuration Registers Physical Memory Map 0xFFFFFFFF Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. "Memory Organization" (DS61115)) and can be changed by initialization code provided by end-user development tools (refer to the specific development tool documentation for information). (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 31 PIC32MX3XX/4XX 4.1.1 PERIPHERAL REGISTERS LOCATIONS Table 4-1 through Table 4-25 contain the peripheral address maps for the PIC32MX3XX/4XX device. Peripherals located on the PB Bus are mapped to 512 byte boundaries. Peripherals on the FPB Bus are mapped to 4 Kbyte boundaries. DS61143F-page 32 Preliminary (c) 2009 Microchip Technology Inc. TABLE 4-1: SFR Virtual Addr SFR Name BUS MATRIX REGISTERS MAP Bits 31/15 31:16 -- -- -- -- -- (c) 2009 Microchip Technology Inc. Bits 30/14 -- -- -- -- -- Bits 29/13 -- -- -- -- -- Bits 28/12 -- -- -- -- -- Bits 27/11 -- -- -- -- -- Bits 26/10 BMX CHEDMA -- -- -- -- Bits 25/9 -- -- -- -- -- Bits 24/8 -- -- -- -- -- Bits 23/7 -- -- -- -- -- Bits 22/6 -- BMX WSDRM -- -- -- Bits 21/5 -- -- -- -- -- Bits 20/4 BMX ERRIXI -- -- -- -- Bits 19/3 BMX ERRICD -- -- -- -- Bits 18/2 BMX ERRDMA Bits 17/1 BMX ERRDS Bits 16/0 BMX ERRIS BF88_2000 BMXCON(1) 15:0 BF88_2010 BF88_2020 BF88_2030 BMX DKPBA(1) BMX DUDBA(1) BMX DUPBA(1) 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 -- -- -- -- -- BMXARB<2:0> -- -- -- -- -- -- -- -- -- BMXDKPBA<15:0> BMXDUDBA<15:0> BMXDUPBA<15:0> BMXDRMSZ<31:0> -- -- -- -- -- -- -- BMXPUPBA<19:16> BF88_2040 BMXDRMSZ BF88_2050 BMX PUPBA(1) BMXPUPBA<15:0> BMXPFMSZ<31:0> BF88_2060 BMXPFMSZ Preliminary DS61143F-page 33 BF88_2070 Legend: Note 1: BMX BOOTSZ BMXBOOTSZ<31:0> 15:0 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. This register has corresponding CLR, SET, and INV Registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. TABLE 4-2: SFR Virtual Addr BF88_1000 BF88_1010 BF88_1020 BF88_1030 BF88_1040 Legend: Note 1: 2: 3: 4: INTERRUPT REGISTERS MAP(1) Bits 31/15 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 I2C1MIF INT3IF -- I2C1SIF OC3IF -- I2C1BIF IC3IF -- U1TXIF T3IF -- U1RXIF INT2IF -- U1EIF OC2IF -- SPI1RXIF IC2IF USBIF(4) -- -- -- -- SFR Name INTCON INTSTAT IPTMR IFS0 IFS1 Bits 30/14 -- FRZ -- -- Bits 29/13 -- -- -- -- Bits 28/12 -- MVEC -- -- Bits 27/11 -- -- -- -- Bits 26/10 -- -- Bits 25/9 -- TRC<2:0> -- RIPL<2:0> Bits 24/8 -- -- Bits 23/7 -- -- -- -- Bits 22/6 -- -- -- -- Bits 21/5 -- -- -- Bits 20/4 -- INT4EP -- Bits 19/3 -- INT3EP -- Bits 18/2 -- INT2EP -- Bits 17/1 -- INT1EP -- Bits 16/0 SS0 INT0EP -- PIC32MX3XX/4XX VEC<5:0> IPTMR<31:0> SPI1TXIF T2IF FCEIF SPI1EIF INT1IF -- OC5IF OC1IF -- IC5IF IC1IF -- T5IF T1IF -- INT4IF INT0IF OC4IF CS1IF IC4IF CS0IF T4IF CTIF DMA3IF(2) DMA2IF(2) DMA1IF(2) DMA0IF(2) 15:0 RTCCIF FSCMIF I2C2MIF I2C2SIF I2C2BIF U2TXIF U2RXIF U2EIF SPI2RXIF(3) SPI2TXIF(3) SPI2EIF(3) CMP2IF CMP1IF PMPIF AD1IF CNIF x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. These bits are not present on PIC32MX320FXXXX/420FXXXX devices. These bits are not present on PIC32MX420FXXXX/440FXXXX devices. These bits are not present on PIC32MX320FXXXX/340FXXXX/360FXXXX devices. TABLE 4-2: SFR Virtual Addr BF88_1060 BF88_1070 BF88_1090 BF88_10A0 BF88_10B0 BF88_10C0 BF88_10D0 BF88_10E0 BF88_10F0 BF88_1100 BF88_1110 BF88_1120 BF88_1140 Legend: Note 1: INTERRUPT REGISTERS MAP(1) (CONTINUED) Bits 31/15 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 I2C1MIE INT3IE -- RTCCIE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- DS61143F-page 34 PIC32MX3XX/4XX SFR Name IEC0 IEC1 IPC0 IPC1 IPC2 IPC3 IPC4 IPC5 IPC6 IPC7 IPC8 IPC9 IPC11 Bits 30/14 I2C1SIE OC3IE -- FSCMIE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bits 29/13 I2C1BIE IC3IE -- I2C2MIE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bits 28/12 U1TXIE T3IE -- I2C2SIE Bits 27/11 U1RXIE INT2IE -- I2C2BIE INT0IP<2:0> CS0IP<2:0> INT1IP<2:0> IC1IP<2:0> INT2IP<2:0> IC2IP<2:0> INT3IP<2:0> IC3IP<2:0> INT4IP<2:0> IC4IP<2:0> SPI1IP<2:0> IC5IP<2:0> AD1IP<2:0> I2C1IP<2:0> SPI2IP<2:0>(3) CMP1IP<2:0> RTCCIP<2:0> I2C2IP<2:0> DMA3IP<2:0>(2) DMA1IP<2:0>(2) Bits 26/10 U1EIE OC2IE -- U2TXIE Bits 25/9 Bits 24/8 Bits 23/7 SPI1EIE INT1IE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bits 22/6 OC5IE OC1IE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bits 21/5 IC5IE IC1IE -- SPI2EIE(3) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bits 20/4 T5IE T1IE -- CMP2IE Bits 19/3 INT4IE INT0IE CMP1IE CS1IP<2:0> CTIP<2:0> OC1IP<2:0> T1IP<2:0> OC2IP<2:0> T2IP<2:0> OC3IP<2:0> T3IP<2:0> OC4IP<2:0> T4IP<2:0> OC5IP<2:0> T5IP<2:0> CNIP<2:0> U1IP<2:0> CMP2IP<2:0> PMPIP<2:0> FSCMIP<2:0> U2IP<2:0> DMA2IP<2:0>(2) DMA0IP<2:0>(2) Bits 18/2 OC4IE CS1IE PMPIE Bits 17/1 IC4IE CS0IE AD1IE Bits 16/0 T4IE CTIE CNIE SPI1RXIE SPI1TXIE IC2IE USBIE U2RXIE T2IE FCEIE U2EIE DMA3IE(2) DMA2IE(2) DMA1IE(2) DMA0IE(2) CS1IS<1:0> CTIS<1:0> OC1IS<1:0> T1IS<1:0> OC2IS<1:0> T2IS<1:0> OC3IS<1:0> T3IS<1:0> OC4IS<1:0> T4IS<1:0> OC5IS<1:0> T5IS<1:0> CNIS<1:0> U1IS<1:0> CMP2IS<1:0> PMPIS<1:0> FSCMIS<1:0> U2IS<1:0> DMA2IS<1:0>(2) DMA0IS<1:0>(2) -- -- -- SPI2RXIE(3) SPI2TXIE(3) INT0IS<1:0> CS0IS<1:0> INT1IS<1:0> IC1IS<1:0> INT2IS<1:0> IC2IS<1:0> INT3IS<1:0> IC3IS<1:0> INT4IS<1:0> IC4IS<1:0> SPI1IS<1:0> IC5IS<1:0> AD1IS<1:0> I2C1IS<1:0> SPI2IS<1:0>(3) CMP1IS<1:0> RTCCIS<1:0> I2C2IS<1:0> DMA3IS<1:0>(2) DMA1IS<1:0>(2) -- -- -- Preliminary (c) 2009 Microchip Technology Inc. -- -- -- -- 2: 3: 4: 15:0 -- -- -- USBIP<2:0>(4) USBIS<1:0>(4) -- -- -- FCEIP<2:0> FCEIS<1:0> x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. These bits are not present on PIC32MX320FXXXX/420FXXXX devices. These bits are not present on PIC32MX420FXXXX/440FXXXX devices. These bits are not present on PIC32MX320FXXXX/340FXXXX/360FXXXX devices. TABLE 4-3: SFR Virtual Addr BF80_0600 BF80_0610 BF80_0620 BF80_0800 BF80_0810 BF80_0820 BF80_0A00 BF80_0A10 BF80_0A20 BF80_0C00 BF80_0C10 BF80_0C20 BF80_0E00 BF80_0E10 BF80_0E20 Legend: Note 1: TIMER1-5 REGISTERS MAP(1) Bits 31/15 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 -- -- -- -- -- -- -- -- ON -- -- FRZ -- -- SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ON -- -- FRZ -- -- SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ON -- -- FRZ -- -- SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ON -- -- FRZ -- -- SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ON -- (c) 2009 Microchip Technology Inc. SFR Name T1CON TMR1 PR1 T2CON TMR2 PR2 T3CON TMR3 PR3 T4CON TMR4 PR4 T5CON TMR5 PR5 Bits 30/14 -- FRZ -- Bits 29/13 -- SIDL -- Bits 28/12 -- TWDIS -- Bits 27/11 -- TWIP -- Bits 26/10 -- -- -- Bits 25/9 -- -- -- Bits 24/8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bits 23/7 -- TGATE -- -- -- TGATE -- -- -- TGATE -- -- -- TGATE -- -- -- TGATE -- -- Bits 22/6 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bits 21/5 -- -- -- -- TCKPS<2:0> -- -- -- TCKPS<2:0> -- -- -- TCKPS<2:0> -- -- -- TCKPS<2:0> -- -- Bits 20/4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bits 19/3 -- -- -- -- -- T32 -- -- -- -- -- -- -- T32 -- -- -- -- -- -- Bits 18/2 -- TSYNC -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bits 17/1 -- TCS -- -- -- TCS -- -- -- TCS -- -- -- TCS -- -- -- TCS -- -- Bits 16/0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TCKPS<1:0> TMR1<15:0> PR1<15:0> TMR2<15:0> PR2<15:0> Preliminary DS61143F-page 35 TMR3<15:0> PR3<15:0> TMR4<15:0> PIC32MX3XX/4XX PR4<15:0> TMR5<15:0> 15:0 PR5<15:0> x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. TABLE 4-4: SFR Virtual Addr SFR Name INPUT CAPTURE1-5 REGISTERS MAP Bits 31/15 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 -- ON -- FRZ -- SIDL -- -- -- -- -- -- -- ICFEDGE -- ON -- FRZ -- SIDL -- -- -- -- -- -- -- ICFEDGE -- ON -- FRZ -- SIDL -- -- -- -- -- -- -- ICFEDGE -- ON -- FRZ -- SIDL -- -- -- -- -- -- -- ICFEDGE -- ON DS61143F-page 36 PIC32MX3XX/4XX Bits 30/14 -- FRZ Bits 29/13 -- SIDL Bits 28/12 -- -- Bits 27/11 -- -- Bits 26/10 -- -- Bits 25/9 -- ICFEDGE Bits 24/8 -- ICC32 Bits 23/7 -- ICTMR Bits 22/6 -- Bits 21/5 -- Bits 20/4 -- ICOV Bits 19/3 -- ICBNE Bits 18/2 -- Bits 17/1 -- ICM<2:0> Bits 16/0 -- BF80_2000 IC1CON(1) BF80_2010 IC1BUF ICI<1:0> IC1BUF<31:0> -- ICC32 -- ICTMR -- ICI<1:0> -- -- ICOV -- ICBNE -- -- ICM<2:0> -- BF80_2200 IC2CON(1) BF80_2210 IC2BUF IC2BUF<31:0> -- ICC32 -- ICTMR -- ICI<1:0> -- -- ICOV -- ICBNE -- -- ICM<2:0> -- BF80_2400 IC3CON(1) BF80_2410 IC3BUF IC3BUF<31:0> -- ICC32 -- ICTMR -- ICI<1:0> -- -- ICOV -- ICBNE -- -- ICM<2:0> -- BF80_2600 IC4CON(1) BF80_2610 IC4BUF IC4BUF<31:0> -- ICC32 -- ICTMR -- ICI<1:0> -- -- ICOV -- ICBNE -- -- ICM<2:0> -- Preliminary (c) 2009 Microchip Technology Inc. BF80_2800 IC5CON(1) BF80_2810 Legend: Note 1: IC5BUF IC5BUF<31:0> 15:0 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. This register has corresponding CLR, SET, and INV Registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. TABLE 4-5: SFR Virtual Addr BF80_3000 BF80_3010 BF80_3020 BF80_3200 BF80_3210 Legend: Note 1: OUTPUT COMPARE 1-5 REGISTERS MAP(1) Bits 31/15 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 -- ON -- FRZ -- SIDL -- -- -- -- -- -- -- -- -- ON SFR Name OC1CON OC1R OC1RS OC2CON OC2R Bits 30/14 -- FRZ Bits 29/13 -- SIDL Bits 28/12 -- -- Bits 27/11 -- -- Bits 26/10 -- -- Bits 25/9 -- -- Bits 24/8 -- -- Bits 23/7 -- -- Bits 22/6 -- -- Bits 21/5 -- OC32 Bits 20/4 -- OCFLT Bits 19/3 -- OCTSEL Bits 18/2 -- Bits 17/1 -- OCM<2:0> Bits 16/0 -- OC1R<31:0> OC1RS<31:0> -- -- -- -- -- -- -- OC32 -- OCFLT -- OCTSEL -- -- OCM<2:0> -- OC2R<31:0> 15:0 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. TABLE 4-5: SFR Virtual Addr BF80_3220 BF80_3400 BF80_3410 BF80_3420 BF80_3600 BF80_3610 BF80_3620 BF80_3800 OUTPUT COMPARE 1-5 REGISTERS MAP(1) (CONTINUED) Bits 31/15 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 -- ON -- FRZ -- SIDL -- -- -- -- -- -- -- -- -- ON -- FRZ -- SIDL -- -- -- -- -- -- -- -- -- ON -- FRZ -- SIDL -- -- -- -- -- -- -- -- (c) 2009 Microchip Technology Inc. SFR Name OC2RS OC3CON OC3R OC3RS OC4CON OC4R OC4RS OC5CON OC5R OC5RS Bits 30/14 Bits 29/13 Bits 28/12 Bits 27/11 Bits 26/10 Bits 25/9 Bits 24/8 Bits 23/7 Bits 22/6 Bits 21/5 Bits 20/4 Bits 19/3 Bits 18/2 Bits 17/1 Bits 16/0 OC2RS<31:0> -- -- -- -- -- -- -- OC32 -- OCFLT -- OCTSEL -- -- OCM<2:0> -- OC3R<31:0> OC3RS<31:0> -- -- -- -- -- -- -- OC32 -- OCFLT -- OCTSEL -- -- OCM<2:0> -- OC4R<31:0> OC4RS<31:0> -- -- -- -- -- -- -- OC32 -- OCFLT -- OCTSEL -- -- OCM<2:0> -- Preliminary DS61143F-page 37 BF80_3810 BF80_3820 Legend: Note 1: OC5R<31:0> OC5RS<31:0> 15:0 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. TABLE 4-6: SFR Virtual Addr BF80_5000 BF80_5010 BF80_5020 BF80_5030 BF80_5040 Legend: Note 1: I2C1-2 REGISTERS MAP(1) Bits 31/15 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 -- ON -- ACKSTAT -- -- -- -- -- PIC32MX3XX/4XX SFR Name I2C1CON I2C1STAT I2C1ADD I2C1MSK I2C1BRG Bits 30/14 -- FRZ -- TRSTAT -- -- -- -- -- Bits 29/13 -- SIDL -- -- -- -- -- -- -- Bits 28/12 -- SCLREL -- -- -- -- -- -- -- Bits 27/11 -- STRICT -- -- -- -- -- -- -- Bits 26/10 -- A10M -- BCL -- -- -- -- -- Bits 25/9 -- DISSLW -- GCSTAT -- -- -- Bits 24/8 -- SMEN -- ADD10 -- -- -- Bits 23/7 -- GCEN -- IWCOL -- -- -- Bits 22/6 -- STREN -- I2COV -- -- -- Bits 21/5 -- ACKDT -- D/A -- -- -- Bits 20/4 -- ACKEN -- P -- -- -- Bits 19/3 -- RCEN -- S -- -- -- Bits 18/2 -- PEN -- R/W -- -- -- Bits 17/1 -- RSEN -- RBF -- -- -- Bits 16/0 -- SEN -- TBF -- -- -- ADD<9:0> MSK<9:0> -- -- -- -- I2C1BRG<11:0> 15:0 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table except I2CxRCV have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. TABLE 4-6: SFR Virtual Addr BF80_5050 BF80_5260 BF80_5200 BF80_5210 BF80_5220 BF80_5230 BF80_5240 I2C1-2 REGISTERS MAP(1) (CONTINUED) Bits 31/15 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 -- -- -- -- -- ON -- ACKSTAT -- -- -- -- -- -- -- -- -- DS61143F-page 38 PIC32MX3XX/4XX SFR Name I2C1TRN I2C1RCV I2C2CON I2C2STAT I2C2ADD I2C2MSK I2C2BRG I2C2TRN I2C2RCV Bits 30/14 -- -- -- -- -- FRZ -- TRSTAT -- -- -- -- -- -- -- -- -- Bits 29/13 -- -- -- -- -- SIDL -- -- -- -- -- -- -- -- -- -- -- Bits 28/12 -- -- -- -- -- SCLREL -- -- -- -- -- -- -- -- -- -- -- Bits 27/11 -- -- -- -- -- STRICT -- -- -- -- -- -- -- -- -- -- Bits 26/10 -- -- -- -- -- A10M -- BCL -- -- -- -- -- -- -- -- Bits 25/9 -- -- -- -- -- DISSLW -- GCSTAT -- -- -- -- -- -- Bits 24/8 -- -- -- -- -- SMEN -- ADD10 -- -- -- -- -- -- Bits 23/7 -- -- -- GCEN -- IWCOL -- -- -- -- -- Bits 22/6 -- -- -- STREN -- I2COV -- -- -- -- -- Bits 21/5 -- -- -- ACKDT -- D/A -- -- -- -- -- Bits 20/4 -- -- -- ACKEN -- P -- -- -- -- -- Bits 19/3 -- -- -- RCEN -- S -- -- -- -- -- Bits 18/2 -- -- -- PEN -- R/W -- -- -- -- -- Bits 17/1 -- -- -- RSEN -- RBF -- -- -- -- -- Bits 16/0 -- -- -- SEN -- TBF -- -- -- -- -- I2CT1DATA<7:0> I2CR1DATA<7:0> ADD<9:0> MSK<9:0> I2C2BRG<11:0> I2CT1DATA<7:0> BF80_5250 BF80_5260 Legend: Note 1: Preliminary (c) 2009 Microchip Technology Inc. 15:0 -- -- -- -- -- -- -- -- I2CR1DATA<7:0> x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table except I2CxRCV have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. TABLE 4-7: SFR Virtual Addr SFR Name UART1-2 REGISTERS MAP Bits 31/15 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 -- -- -- -- -- -- -- -- ON -- -- -- -- -- -- Bits 30/14 -- FRZ -- -- -- -- -- -- Bits 29/13 -- SIDL -- UTXINV -- -- -- -- -- Bits 28/12 -- IREN -- URXEN -- -- -- -- -- Bits 27/11 -- RTSMD -- UTXBRK -- -- -- -- -- Bits 26/10 -- -- -- UTXEN -- -- -- -- -- Bits 25/9 -- -- UTXBF -- -- -- -- -- Bits 24/8 -- ADM_EN TRMT -- TX8 -- RX8 -- -- Bits 23/7 -- WAKE Bits 22/6 -- LPBACK Bits 21/5 -- ABAUD ADDEN -- -- -- -- Bits 20/4 -- RXINV RIDLE -- -- -- -- Bits 19/3 -- BRGH PERR -- -- -- -- Bits 18/2 -- Bits 17/1 -- Bits 16/0 -- STSEL URXDA -- -- -- -- BF80_6000 U1MODE(1) BF80_6010 U1STA(1) UEN<1:0> PDSEL<1:0> FERR -- -- -- -- OERR -- -- -- -- ADDR<7:0> URXISEL<1:0> -- -- -- -- -- -- -- -- UTXISEL<1:0> BF80_6020 U1TXREG BF80_6030 U1RXREG BF80_6040 U1BRG(1) Transmit Register Receive Register BRG<15:0> BF80_6200 U2MODE(1) Legend: Note 1: 15:0 ON FRZ SIDL IREN RTSMD -- UEN<1:0> WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> STSEL x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. This register has corresponding CLR, SET, and INV Registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. TABLE 4-7: SFR Virtual Addr BF80_6210 UART1-2 REGISTERS MAP (CONTINUED) Bits 31/15 31:16 15:0 31:16 15:0 31:16 15:0 31:16 -- -- -- -- -- -- (c) 2009 Microchip Technology Inc. SFR Name U2STA(1) Bits 30/14 -- -- -- -- -- -- Bits 29/13 -- UTXINV -- -- -- -- -- Bits 28/12 -- URXEN -- -- -- -- -- Bits 27/11 -- UTXBRK -- -- -- -- -- Bits 26/10 -- UTXEN -- -- -- -- -- Bits 25/9 -- UTXBF -- -- -- -- -- Bits 24/8 ADM_EN TRMT -- TX8 -- RX8 -- Bits 23/7 Bits 22/6 Bits 21/5 Bits 20/4 Bits 19/3 Bits 18/2 Bits 17/1 Bits 16/0 ADDR<7:0> URXISEL<1:0> -- -- -- -- -- -- ADDEN -- -- -- RIDLE -- -- -- PERR -- -- -- FERR -- -- -- OERR -- -- -- URXDA -- -- -- UTXISEL<1:0> BF80_6220 U2TXREG BF80_6230 U2RXREG BF80_6240 Legend: Note 1: U2BRG(1) Transmit Register Receive Register 15:0 BRG<15:0> x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. This register has corresponding CLR, SET, and INV Registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. TABLE 4-8: SFR Virtual Addr SFR Name SPI1CON SPI1-2 REGISTERS MAP(1,2) Bits 31/15 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 -- -- -- -- -- -- -- -- -- FRMEN ON -- -- -- -- FRZ -- -- -- -- SIDL -- -- -- -- -- DISSDO -- -- -- -- -- MODE32 -- SPIBUSY -- -- -- MODE16 -- -- -- -- -- SMP -- -- -- CKE -- -- -- SSEN -- -- -- CKP -- SPIROV -- MSTEN -- -- FRMEN ON -- -- Bits 30/14 Bits 29/13 Bits 28/12 -- DISSDO -- -- Bits 27/11 -- MODE32 -- SPIBUSY Bits 26/10 -- MODE16 -- -- Bits 25/9 -- SMP -- -- Bits 24/8 -- CKE -- -- Bits 23/7 -- SSEN -- -- Bits 22/6 -- CKP -- SPIROV Bits 21/5 -- MSTEN -- -- Bits 20/4 -- -- -- -- Bits 19/3 -- -- -- SPITBE Bits 18/2 -- -- -- -- Bits 17/1 SPIFE -- -- -- Bits 16/0 -- -- -- SPIRBF BF80_5800 FRMSYNC FRMPOL FRZ -- -- SIDL -- -- Preliminary DS61143F-page 39 BF80_5810 SPI1STAT BF80_5820 BF80_5830 SPI1BUF SPI1BRG DATA<31:0> -- -- -- -- -- BRG<8:0> -- -- -- -- -- -- -- -- SPITBE -- -- -- -- -- -- SPIFE -- -- -- -- PIC32MX3XX/4XX BF80_5A00 SPI2CON BF80_5A10 SPI2STAT BF80_5A20 SPI2BUF FRMSYNC FRMPOL -- -- -- SPIRBF DATA<31:0> -- -- -- -- -- -- -- -- -- BF80_5A30 SPI2BRG Legend: Note 1: 2: 15:0 -- -- -- -- -- -- -- BRG<8:0> x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. SPI2 Module is not present on PIC32MX420FXXXX/440FXXXX devices. TABLE 4-9: SFR Virtual Addr SFR Name ADC REGISTERS MAP Bits 31/15 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 -- ON -- VCFG2 -- ADRC CH0NB -- -- PCFG15 -- CSSL15 DS61143F-page 40 PIC32MX3XX/4XX Bits 30/14 -- FRZ -- VCFG1 -- -- -- -- -- PCFG14 -- CSSL14 Bits 29/13 -- SIDL -- VCFG0 -- -- -- -- -- PCFG13 -- CSSL13 Bits 28/12 -- -- -- OFFCAL -- -- -- -- PCFG12 -- CSSL12 Bits 27/11 -- -- -- -- -- Bits 26/10 -- -- CSCNA -- SAMC<4:0> Bits 25/9 -- FORM<2:0> -- -- -- Bits 24/8 -- -- -- -- Bits 23/7 -- -- BUFS -- CH0NA Bits 22/6 -- SSRC<2:0> -- -- -- -- -- -- PCFG6 -- CSSL6 Bits 21/5 -- -- -- -- -- -- PCFG5 -- CSSL5 Bits 20/4 -- CLRASAM -- -- -- -- -- PCFG4 -- CSSL4 Bits 19/3 -- -- -- -- Bits 18/2 -- ASAM -- -- Bits 17/1 -- SAMP -- BUFM -- Bits 16/0 -- DONE -- ALTS -- BF80_9000 AD1CON1(1) BF80_9010 AD1CON2(1) BF80_9020 AD1CON3(1) BF80_9040 AD1CHS(1) BF80_9060 AD1PCFG (1) SMPI<3:0> ADCS<7:0> CH0SB<3:0> -- -- PCFG11 -- CSSL11 -- -- PCFG10 -- CSSL10 -- -- PCFG9 -- CSSL9 -- -- PCFG8 -- CSSL8 CH0SA<3:0> -- -- PCFG3 -- CSSL3 -- -- PCFG2 -- CSSL2 -- -- PCFG1 -- CSSL1 -- -- PCFG0 -- CSSL0 -- -- PCFG7 -- CSSL7 BF80_9050 AD1CSSL(1) BF80_9070 ADC1BUF0 BF80_9080 ADC1BUF1 BF80_9090 ADC1BUF2 BF80_90A0 ADC1BUF3 BF80_90B0 ADC1BUF4 BF80_90C0 ADC1BUF5 BF80_90D0 ADC1BUF6 BF80_90E0 ADC1BUF7 ADC Result Word 0 (ADC1BUF0<31:0>) ADC Result Word 1 (ADC1BUF1<31:0>) ADC Result Word 2 (ADC1BUF2<31:0>) ADC Result Word 3 (ADC1BUF3<31:0>) ADC Result Word 4 (ADC1BUF4<31:0>) ADC Result Word 5 (ADC1BUF5<31:0>) ADC Result Word 6 (ADC1BUF6<31:0>) ADC Result Word 7 (ADC1BUF7<31:0>) ADC Result Word 8 (ADC1BUF8<31:0>) ADC Result Word 9 (ADC1BUF9<31:0>) ADC Result Word A (ADC1BUFA<31:0>) Preliminary (c) 2009 Microchip Technology Inc. BF80_90F0 ADC1BUF8 BF80_9100 ADC1BUF9 BF80_9110 ADC1BUFA BF80_9120 ADC1BUFB Legend: Note 1: ADC Result Word B (ADC1BUFB<31:0>) 15:0 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. This register has corresponding CLR, SET, and INV Registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. TABLE 4-9: SFR Virtual Addr SFR Name ADC REGISTERS MAP (CONTINUED) Bits 31/15 31:16 15:0 31:16 15:0 31:16 15:0 31:16 (c) 2009 Microchip Technology Inc. Bits 30/14 Bits 29/13 Bits 28/12 Bits 27/11 Bits 26/10 Bits 25/9 Bits 24/8 Bits 23/7 Bits 22/6 Bits 21/5 Bits 20/4 Bits 19/3 Bits 18/2 Bits 17/1 Bits 16/0 BF80_9130 ADC1BUFC BF80_9140 ADC1BUFD BF80_9150 ADC1BUFE BF80_9160 ADC1BUFF Legend: Note 1: ADC Result Word C (ADC1BUFC<31:0>) ADC Result Word D (ADC1BUFD<31:0>) ADC Result Word E (ADC1BUFE<31:0>) ADC Result Word F (ADC1BUFF<31:0>) 15:0 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. This register has corresponding CLR, SET, and INV Registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. TABLE 4-10: SFR Virtual Addr SFR Name DMA GLOBAL REGISTERS MAP FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX DEVICES ONLY Bits 31/15 31:16 15:0 31:16 15:0 31:16 -- ON -- -- Bits 30/14 -- FRZ -- -- Bits 29/13 -- SIDL -- -- Bits 28/12 -- SUSPEND -- -- Bits 27/11 -- -- -- -- Bits 26/10 -- -- -- -- Bits 25/9 -- -- -- -- Bits 24/8 -- -- -- -- Bits 23/7 -- -- -- -- Bits 22/6 -- -- -- -- Bits 21/5 -- -- -- -- Bits 20/4 -- -- -- -- Bits 19/3 -- -- -- RDWR Bits 18/2 -- -- -- -- Bits 17/1 -- -- -- Bits 16/0 -- -- -- Preliminary DS61143F-page 41 BF88_3000 DMACON(1) BF88_3010 DMASTAT BF88_3020 DMAADDR Legend: Note 1: DMACH<1:0> DMAADDR<31:0> 15:0 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. This register has corresponding CLR, SET, and INV Registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. PIC32MX3XX/4XX TABLE 4-11: SFR Virtual Addr SFR Name DMA CRC REGISTERS MAP FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX DEVICES ONLY(1) Bits 31/15 31:16 15:0 31:16 15:0 31:16 -- -- -- -- -- -- -- -- -- -- Bits 30/14 -- -- -- Bits 29/13 -- -- -- Bits 28/12 -- -- -- Bits 27/11 -- -- Bits 26/10 -- -- Bits 25/9 -- -- Bits 24/8 -- -- -- Bits 23/7 -- CRCEN -- -- Bits 22/6 -- CRCAPP -- -- Bits 21/5 -- -- -- -- Bits 20/4 -- -- -- -- Bits 19/3 -- -- -- -- Bits 18/2 -- -- -- -- Bits 17/1 -- -- -- Bits 16/0 -- -- -- BF88_3030 DCRCCON BF88_3040 DCRCDATA BF88_3050 DCRCXOR Legend: Note 1: PLEN<3:0> CRCCH<1:0> DCRCDATA<15:0> 15:0 DCRCXOR<15:0> x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. TABLE 4-12: SFR Virtual Addr SFR Name DMA CHANNELS 0-3 REGISTERS MAP FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX DEVICES ONLY(1) Bits 31/15 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- DS61143F-page 42 PIC32MX3XX/4XX Bits 30/14 -- -- -- Bits 29/13 -- -- -- Bits 28/12 -- -- -- -- -- Bits 27/11 -- -- -- -- -- Bits 26/10 -- -- -- -- -- Bits 25/9 -- -- -- -- -- Bits 24/8 -- CHCHNS -- Bits 23/7 -- CHEN CFORCE Bits 22/6 -- CHAED CABORT CHSHIE CHSHIF Bits 21/5 -- CHCHN PATEN CHDDIE CHDDIF Bits 20/4 -- CHAEN SIRQEN CHDHIE CHDHIF Bits 19/3 -- -- AIRQEN CHBCIE CHBCIF Bits 18/2 -- CHEDET -- CHCCIE CHCCIF Bits 17/1 -- Bits 16/0 -- BF88_3060 DCH0CON BF88_3070 DCH0ECON BF88_3080 DCH0INT CHPRI<1:0> -- CHTAIE CHTAIF -- CHERIE CHERIF CHAIRQ<7:0> CHSDIE CHSDIF CHSIRQ<7:0> -- -- BF88_3090 DCH0SSA BF88_30A0 DCH0DSA BF88_30B0 DCH0SSIZ BF88_30C0 DCH0DSIZ CHSSA<31:0> CHDSA<31:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CHCHNS -- CFORCE -- -- CHSDIE CHSDIF CABORT CHSHIE CHSHIF PATEN CHDDIE CHDDIF -- CHEN -- CHAED -- CHCHN -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CHAEN SIRQEN CHDHIE CHDHIF -- -- -- -- -- -- -- -- -- AIRQEN CHBCIE CHBCIF -- -- -- -- -- -- -- -- CHEDET -- CHCCIE CHCCIF -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CHSSIZ<7:0> CHDSIZ<7:0> CHSTR<7:0> CHDPTR<7:0> CHCSIZ<7:0> CHCPTR<7:0> CHPDAT<7:0> CHPRI<1:0> -- CHTAIE CHTAIF -- CHERIE CHERIF Preliminary (c) 2009 Microchip Technology Inc. BF88_30D0 DCH0SPTR BF88_30E0 DCH0DPTR BF88_30F0 DCH0CSIZ BF88_3100 DCH0CPTR BF88_3110 DCH0DAT BF88_3120 DCH1CON BF88_3130 DCH1ECON BF88_3140 DCH1INT CHAIRQ<7:0> CHSIRQ<7:0> BF88_3150 DCH1SSA BF88_3160 DCH1DSA Legend: Note 1: CHSSA<31:0> CHDSA<31:0> 15:0 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers except DCHxSPTR, DCHxDPTR, and DCHxCPTR have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. TABLE 4-12: SFR Virtual Addr SFR Name DMA CHANNELS 0-3 REGISTERS MAP (CONTINUED)FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX DEVICES ONLY(1) (CONTINUED) Bits 31/15 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- (c) 2009 Microchip Technology Inc. Bits 30/14 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bits 29/13 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bits 28/12 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bits 27/11 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bits 26/10 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bits 25/9 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bits 24/8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CHCHNS -- Bits 23/7 -- -- -- -- -- -- -- -- CHEN CFORCE Bits 22/6 -- -- -- -- -- -- -- -- CHAED CABORT CHSHIE CHSHIF Bits 21/5 -- -- -- -- -- -- -- -- CHCHN PATEN CHDDIE CHDDIF Bits 20/4 -- -- -- -- -- -- -- -- CHAEN SIRQEN CHDHIE CHDHIF Bits 19/3 -- -- -- -- -- -- -- -- -- AIRQEN CHBCIE CHBCIF Bits 18/2 -- -- -- -- -- -- -- -- CHEDET -- CHCCIE CHCCIF Bits 17/1 -- -- -- -- -- -- -- -- Bits 16/0 -- -- -- -- -- -- -- -- BF88_3170 DCH1SSIZ BF88_3180 DCH1DSIZ BF88_3190 DCH1SPTR BF88_31A0 DCH1DPTR BF88_31B0 DCH1CSIZ BF88_31C0 DCH1CPTR BF88_31D0 DCH1DAT CHSSIZ<7:0> CHDSIZ<7:0> CHSPTR<7:0> CHDPTR<7:0> CHCSIZ<7:0> CHCPTR<7:0> CHPDAT<7:0> CHPRI<1:0> -- CHTAIE CHTAIF -- CHERIE CHERIF Preliminary DS61143F-page 43 BF88_31E0 DCH2CON BF88_31F0 DCH2ECON BF88_3200 DCH2INT CHAIRQ<7:0> CHSDIE CHSDIF CHSIRQ<7:0> -- -- BF88_3210 DCH2SSA BF88_3220 DCH2DSA BF88_3230 DCH2SSIZ BF88_3240 DCH2DSIZ BF88_3250 DCH2SPTR BF88_3260 DCH2DPTR BF88_3270 DCH2CSIZ Legend: Note 1: CHSSA<31:0> PIC32MX3XX/4XX CHDSA<31:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CHSSIZ<7:0> CHDSIZ<7:0> CHSPTR<7:0> CHDPTR<7:0> 15:0 -- -- -- -- -- -- -- -- CHCSIZ<7:0> x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers except DCHxSPTR, DCHxDPTR, and DCHxCPTR have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. TABLE 4-12: SFR Virtual Addr SFR Name DMA CHANNELS 0-3 REGISTERS MAP (CONTINUED)FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX DEVICES ONLY(1) (CONTINUED) Bits 31/15 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- DS61143F-page 44 PIC32MX3XX/4XX Bits 30/14 -- -- -- -- -- -- -- Bits 29/13 -- -- -- -- -- -- -- Bits 28/12 -- -- -- -- -- -- -- -- -- Bits 27/11 -- -- -- -- -- -- -- -- -- Bits 26/10 -- -- -- -- -- -- -- -- -- Bits 25/9 -- -- -- -- -- -- -- -- -- Bits 24/8 -- -- -- -- -- CHCHNS -- Bits 23/7 -- -- -- CHEN CFORCE Bits 22/6 -- -- -- CHAED CABORT CHSHIE CHSHIF Bits 21/5 -- -- -- CHCHN PATEN CHDDIE CHDDIF Bits 20/4 -- -- -- CHAEN SIRQEN CHDHIE CHDHIF Bits 19/3 -- -- -- -- AIRQEN CHBCIE CHBCIF Bits 18/2 -- -- -- CHEDET -- CHCCIE CHCCIF Bits 17/1 -- -- -- Bits 16/0 -- -- -- BF88_3280 DCH2CPTR BF88_3290 DCH2DAT BF88_32A0 DCH3CON BF88_32B0 DCH3ECON BF88_32C0 DCH3INT BF88_32D0 DCH3SSA BF88_32E0 DCH3DSA CHCPTR<7:0> CHPDAT<7:0> CHPRI<1:0> -- CHTAIE CHTAIF -- CHERIE CHERIF CHAIRQ<7:0> CHSDIE CHSDIF CHSIRQ<7:0> -- -- CHSSA<31:0> CHDSA<31:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Preliminary (c) 2009 Microchip Technology Inc. BF88_32F0 DCH3SSIZ BF88_3300 DCH3DSIZ BF88_3310 DCH3SPTR BF88_3320 DCH3DPTR BF88_3330 DCH3CSIZ BF88_3340 DCH3CPTR BF88_3350 DCH3DAT Legend: Note 1: CHSSIZ<7:0> CHDSIZ<7:0> CHSTR<7:0> CHDPTR<7:0> CHCSIZ<7:0> CHCPTR<7:0> 15:0 -- -- -- -- -- -- -- -- CHPDAT<7:0> x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers except DCHxSPTR, DCHxDPTR, and DCHxCPTR have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. TABLE 4-13: SFR Virtual Addr SFR Name COMPARATOR REGISTERS MAP(1) Bits 31/15 31:16 15:0 31:16 15:0 31:16 -- ON -- ON -- (c) 2009 Microchip Technology Inc. Bits 30/14 -- COE -- COE -- Bits 29/13 -- CPOL -- CPOL -- Bits 28/12 -- -- -- -- -- Bits 27/11 -- -- -- -- -- Bits 26/10 -- -- -- -- -- Bits 25/9 -- -- -- -- -- Bits 24/8 -- COUT -- COUT -- Bits 23/7 -- -- -- Bits 22/6 -- -- -- Bits 21/5 -- -- -- -- -- Bits 20/4 -- CREF -- CREF -- Bits 19/3 -- -- -- -- -- Bits 18/2 -- -- -- -- -- Bits 17/1 -- -- -- Bits 16/0 -- -- -- BF80_A000 CM1CON BF80_A010 CM2CON BF80_A060 Legend: Note 1: CMSTAT EVPOL<1:0> EVPOL<1:0> CCH<1:0> CCH<1:0> 15:0 -- FRZ SIDL -- -- -- -- -- -- -- -- -- -- -- C2OUT C1OUT x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. TABLE 4-14: SFR Virtual Addr BF80_9800 Legend: Note 1: COMPARATOR VOLTAGE REFERENCE REGISTERS MAP(1) Bits 31/15 31:16 -- SFR Name CVRCON Bits 30/14 -- Bits 29/13 -- Bits 28/12 -- Bits 27/11 -- Bits 26/10 -- Bits 25/9 -- Bits 24/8 -- Bits 23/7 -- Bits 22/6 -- Bits 21/5 -- Bits 20/4 -- Bits 19/3 -- Bits 18/2 -- Bits 17/1 -- Bits 16/0 -- 15:0 ON -- -- -- -- -- -- -- -- CVROE CVRR CVRSS CVR<3:0> x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. Preliminary DS61143F-page 45 TABLE 4-15: SFR Virtual Addr SFR Name FLASH CONTROLLER REGISTERS MAP Bits 31/15 31:16 -- NVMWR Bits 30/14 -- NVM WREN Bits 29/13 -- NVMERR Bits 28/12 -- LVDERR Bits 27/11 -- LVDSTAT Bits 26/10 -- -- Bits 25/9 -- -- Bits 24/8 -- -- Bits 23/7 -- -- Bits 22/6 -- -- Bits 21/5 -- -- Bits 20/4 -- -- Bits 19/3 -- Bits 18/2 -- Bits 17/1 -- Bits 16/0 -- BF80_F400 NVMCON(1) PIC32MX3XX/4XX 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 NVMOP<3:0> BF80_F410 NVMKEY NVMKEY<31:0> NVMADDR<31:0> NVMDATA<31:0> BF80_F420 NVMADDR(1) BF80_F430 NVMDATA BF80_F440 Legend: Note 1: NVMSRC ADDR NVMSRCADDR<31:0> 15:0 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. This register has corresponding CLR, SET, and INV Registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. TABLE 4-16: SFR Virtual Addr SFR Name SYSTEM CONTROL REGISTERS MAP(1) Bits 31/15 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 -- -- -- -- -- ON -- -- -- -- -- -- -- -- -- -- DS61143F-page 46 PIC32MX3XX/4XX Bits 30/14 -- Bits 29/13 Bits 28/12 PLLODIV<2:0> Bits 27/11 Bits 26/10 Bits 25/9 RCDIV<2:0> Bits 24/8 Bits 23/7 -- CLKLOCK Bits 22/6 SOSCRDY ULOCK -- -- -- -- SWR -- Bits 21/5 -- LOCK -- -- -- -- -- Bits 20/4 Bits 19/3 Bits 18/2 Bits 17/1 PLLMULT<2:0> Bits 16/0 BF80_F000 OSCCON BF80_F010 OSCTUN PBDIV<1:0> SLPEN -- -- SWDTPS<4:0> -- WDTO -- -- SLEEP -- -- IDLE -- CF -- -- -- -- COSC<2:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- NOSC<2:0> -- -- -- -- -- CM -- -- -- -- -- -- VREGS -- UFRCEN SOSCEN -- -- -- -- BOR -- OSWEN -- -- WDTCLR -- POR -- -- -- -- -- -- EXTR -- TUN<5:0> BF80_0000 WDTCON BF80_F600 BF80_F610 Legend: Note 1: RCON RSWRST 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SWRST x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. TABLE 4-17: SFR Virtual Addr SFR Name PORT A-G REGISTERS MAP(11) Bits 31/15 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 -- -- -- -- -- -- -- -- TRISA15 -- RA15 -- LATA15 -- ODCA15 -- Bits 30/14 -- TRISA14 -- RA14 -- LATA14 -- ODCA14 -- Bits 29/13 -- -- -- -- -- -- -- -- -- Bits 28/12 -- -- -- -- -- -- -- -- -- Bits 27/11 -- -- -- -- -- -- -- -- -- Bits 26/10 -- TRISA10 -- RA10 -- LATA10 -- ODCA10 -- Bits 25/9 -- TRISA9 -- RA9 -- LATA9 -- ODCA9 -- Bits 24/8 -- -- -- -- -- -- -- -- -- -- Bits 23/7 -- -- -- -- -- -- Bits 22/6 -- -- -- -- -- -- Bits 21/5 -- -- -- -- -- -- Bits 20/4 -- -- Bits 19/3 -- -- Bits 18/2 -- -- -- -- -- -- Bits 17/1 -- -- -- -- -- -- Bits 16/0 -- -- -- -- -- -- Preliminary (c) 2009 Microchip Technology Inc. BF88_6000 TRISA(1,2,3) BF88_6010 PORTA(1,2,3) BF88_6020 LATA(1,2,3) BF88_6030 ODCA(1,2,3) BF88_6040 TRISB(4,5) BF88_6050 PORTB(4,5) Legend: Note 1: 2: 3: 4: 5: 6: 7: 8: 9: 10: 11: TRISA<7:0> RA<7:0> -- -- -- -- -- -- -- -- LATA<7:0> ODCA<7:0> TRISB<15:0> 15:0 RB<15:0> x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TRISA, PORTA, LATA and ODCA registers are not implemented on 64-pin devices, and read as `0'. JTAG program/debug port is multiplexed with port pins RA0, RA1, RA4 and RA5 on 100-pin devices. At power-on-reset, these pins are controlled by the JTAG port. To use these pins for general purpose I/O, the user's application code must clear JTAGEN (DDPCON<3>) bit = 0. To use these pins for JTAG program/debug, the user's application code must maintain JTAGEN bit = 1. On specific 100-pin devices, the instruction TRACE port is multiplexed with PORTA pins RA6, RA7; PORTG pins RG12, RG13 and RG14. At Power-on Reset, these pins are general purpose I/O pins. To maintain these pins as general purpose I/O pins, the user's application code must maintain TROEN (DDPCON<2>) bit = 0. To use these pins as instruction TRACE pins, TROEN must be set = 1. JTAG program/debug port is multiplexed with port pins RB10, RB11, RB12 and RB13 on 64-pin devices. At power-on-reset, these pins are controlled by the JTAG port. To use these pins for general purpose I/O, the user's application code must clear JTAGEN (DDPCON<3>) bit = 0. To use these pins for JTAG program/debug, the user's application code must maintain JTAGEN bit = 1. Port Pin RB3 is not available as a general purpose I/O pin when the USB module is enabled. Not implemented on 64-pin devices. Read as `0'. Not implemented on 64-pin USB devices. Read as `0'. Not implemented on 100-pin USB devices. Read as `0'. Not available as a general purpose I/O pin when USB module is enabled. Not available as a general purpose I/O pin when USB module is enabled. Input only when the USB module is disabled. All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. TABLE 4-17: SFR Virtual Addr BF88_6060 PORT A-G REGISTERS MAP(11) (CONTINUED) Bits 31/15 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 31:16 15:0 31:16 15:0 31:16 31:16 15:0 31:16 15:0 31:16 -- TRISC15 -- RC15 -- LATC15 -- ODCC15 -- -- RD15(6) -- LAT15(6) -- -- -- -- -- -- -- TRISC14 -- RC14 -- LATC14 -- ODCC14 -- -- RD14(6) -- LAT14(6) -- -- -- -- -- -- -- TRISC13 -- RC13 -- LATC13 -- ODCC13 -- -- RD13(6) -- LAT13(6) -- -- -- -- -- -- -- TRISC12 -- RC12 -- LATC12 -- ODCC12 -- -- RD12(6) -- LAT12(6) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- RE9(6) -- -- -- -- -- -- -- -- -- (c) 2009 Microchip Technology Inc. SFR Name LATB(4,5) Bits 30/14 -- Bits 29/13 -- Bits 28/12 -- Bits 27/11 -- Bits 26/10 -- Bits 25/9 -- Bits 24/8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- RE8(6) -- Bits 23/7 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bits 22/6 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bits 21/5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bits 20/4 -- -- -- -- RC4(6) -- LATC4(6) -- -- -- Bits 19/3 -- -- -- -- RC3(6) -- LATC3(6) -- -- -- Bits 18/2 -- -- -- -- RC2(6) -- LATC2(6) -- -- -- -- -- -- -- -- Bits 17/1 -- -- -- -- RC1(6) -- LATC1(6) -- -- -- -- -- -- -- -- Bits 16/0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- LATB<15:0> ODCB<15:0> TRISC4(6) TRISC3(6) TRISC2(6) TRISC1(6) BF88_6070 ODCB(4,5) BF88_6080 BF88_6090 BF88_60A0 BF88_60B0 BF88_60C0 BF88_60D0 BF88_60E0 BF88_60F0 BF88_6100 BF88_6110 BF88_6120 Legend: Note 1: 2: 3: 4: 5: 6: 7: 8: 9: 10: 11: TRISC PORTC LATC ODCC TRISD PORTD LATD ODCD TRISE PORTE LATE ODCC4(6) ODCC3(6) ODCC2(6) ODCC1(6) TRISD<7:0> RD<7:0> -- -- -- -- RE<7:0> -- -- -- -- -- -- LATD<7:0> ODCD<7:0> TRISE<7:0> 15:0 TRISD15(6) TRISD14(6) TRISD13(6) TRISD12(6) TRISD<11:8> RD<11:8> LATD<11:8> ODCD<11:8> TRISE9(6) TRISE8(6) Preliminary DS61143F-page 47 15:0 ODCD15(6) ODCD14(6) ODCD13(6) ODCD12(6) PIC32MX3XX/4XX 15:0 -- -- -- -- -- -- LATE9(6) LATE8(6) LATE<7:0> x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TRISA, PORTA, LATA and ODCA registers are not implemented on 64-pin devices, and read as `0'. JTAG program/debug port is multiplexed with port pins RA0, RA1, RA4 and RA5 on 100-pin devices. At power-on-reset, these pins are controlled by the JTAG port. To use these pins for general purpose I/O, the user's application code must clear JTAGEN (DDPCON<3>) bit = 0. To use these pins for JTAG program/debug, the user's application code must maintain JTAGEN bit = 1. On specific 100-pin devices, the instruction TRACE port is multiplexed with PORTA pins RA6, RA7; PORTG pins RG12, RG13 and RG14. At Power-on Reset, these pins are general purpose I/O pins. To maintain these pins as general purpose I/O pins, the user's application code must maintain TROEN (DDPCON<2>) bit = 0. To use these pins as instruction TRACE pins, TROEN must be set = 1. JTAG program/debug port is multiplexed with port pins RB10, RB11, RB12 and RB13 on 64-pin devices. At power-on-reset, these pins are controlled by the JTAG port. To use these pins for general purpose I/O, the user's application code must clear JTAGEN (DDPCON<3>) bit = 0. To use these pins for JTAG program/debug, the user's application code must maintain JTAGEN bit = 1. Port Pin RB3 is not available as a general purpose I/O pin when the USB module is enabled. Not implemented on 64-pin devices. Read as `0'. Not implemented on 64-pin USB devices. Read as `0'. Not implemented on 100-pin USB devices. Read as `0'. Not available as a general purpose I/O pin when USB module is enabled. Not available as a general purpose I/O pin when USB module is enabled. Input only when the USB module is disabled. All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. TABLE 4-17: SFR Virtual Addr BF88_6130 BF88_6140 BF88_6150 BF88_6160 BF88_6170 BF88_6180 BF88_6190 BF88_61A0 BF88_61B0 Legend: Note 1: 2: 3: 4: 5: 6: 7: 8: 9: 10: 11: PORT A-G REGISTERS MAP(11) (CONTINUED) Bits 31/15 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 31:16 15:0 31:16 31:16 -- -- -- -- -- -- -- -- -- -- -- -- RG15(6) -- -- DS61143F-page 48 PIC32MX3XX/4XX SFR Name ODCE TRISF PORTF LATF ODCF TRISG PORTG LATG ODCG Bits 30/14 -- -- -- -- -- -- -- -- -- -- -- -- RG14(6) -- -- Bits 29/13 -- -- -- -- RF13(6) -- -- -- -- RG13(6) -- -- Bits 28/12 -- -- -- -- RF12(6) -- -- -- -- RG12(6) -- -- Bits 27/11 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bits 26/10 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bits 25/9 -- -- -- -- -- -- -- -- -- -- TRISG9 -- RG9 -- LATG9 -- Bits 24/8 -- -- -- RF8(6) -- LATF8(6) -- -- TRISG8 -- RG8 -- LATG8 -- Bits 23/7 -- -- -- RF7(6,8) -- -- -- TRISG7 -- RG7 -- LATG7 -- Bits 22/6 -- -- -- RF6(7,8) -- -- -- TRISG6 -- RG6 -- LATG6 -- Bits 21/5 -- -- TRISF5 -- RF5 -- LATF5 -- ODCF5 -- -- -- -- -- -- -- Bits 20/4 -- -- TRISF4 -- RF4 -- LATF4 -- ODCF4 -- -- -- -- -- -- -- Bits 19/3 -- -- TRISF3 -- RF3(9) -- LATF3 -- ODCF3 -- TRISG3 -- RG3(10) -- LATG3 -- Bits 18/2 -- -- TRISF2(7) -- RF2(7) -- LATF2(7) -- ODCF2(7) -- TRISG2 -- RG2(10) -- LATG2 -- Bits 17/1 -- -- TRISF1 -- RF1 -- LATF1 -- ODCF1 -- -- RG1(6) -- LATG1(6) -- Bits 16/0 -- -- TRISF0 -- RF0 -- LATF0 -- ODCF0 -- -- RG0(6) -- LATG0(6) -- ODCE9(6) ODCE8(6) TRISF8(6) TRISF7(6,8) TRISF6(7,8) ODCE<7:0> TRISF13(6) TRISF12(6) LATF13(6) LATF12(6) ODCF13(6) ODCF12(6) LATF7(6,8) LATF6(7,8) ODCF8(6) ODCF7(6,8) ODCF6(7,8) 15:0 TRISG15(6) TRISG14(6) TRISG13(6) TRISG12(6) TRISG1(6) TRISG0(6) Preliminary (c) 2009 Microchip Technology Inc. 15:0 LATG15(6) LATG14(6) LATG13(6) LATG12(6) 15:0 ODCG15(6) ODCG14(6) ODCG13(6) ODCG12(6) -- -- ODCG9 ODCG8 ODCG7 ODCG6 -- -- ODCG3 ODCG2 ODCG1(6) ODCG0(6) x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TRISA, PORTA, LATA and ODCA registers are not implemented on 64-pin devices, and read as `0'. JTAG program/debug port is multiplexed with port pins RA0, RA1, RA4 and RA5 on 100-pin devices. At power-on-reset, these pins are controlled by the JTAG port. To use these pins for general purpose I/O, the user's application code must clear JTAGEN (DDPCON<3>) bit = 0. To use these pins for JTAG program/debug, the user's application code must maintain JTAGEN bit = 1. On specific 100-pin devices, the instruction TRACE port is multiplexed with PORTA pins RA6, RA7; PORTG pins RG12, RG13 and RG14. At Power-on Reset, these pins are general purpose I/O pins. To maintain these pins as general purpose I/O pins, the user's application code must maintain TROEN (DDPCON<2>) bit = 0. To use these pins as instruction TRACE pins, TROEN must be set = 1. JTAG program/debug port is multiplexed with port pins RB10, RB11, RB12 and RB13 on 64-pin devices. At power-on-reset, these pins are controlled by the JTAG port. To use these pins for general purpose I/O, the user's application code must clear JTAGEN (DDPCON<3>) bit = 0. To use these pins for JTAG program/debug, the user's application code must maintain JTAGEN bit = 1. Port Pin RB3 is not available as a general purpose I/O pin when the USB module is enabled. Not implemented on 64-pin devices. Read as `0'. Not implemented on 64-pin USB devices. Read as `0'. Not implemented on 100-pin USB devices. Read as `0'. Not available as a general purpose I/O pin when USB module is enabled. Not available as a general purpose I/O pin when USB module is enabled. Input only when the USB module is disabled. All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. TABLE 4-18: SFR Virtual Addr BF88_61C0 Legend: Note 1: 2: CHANGE NOTICE AND PULL-UP REGISTERS MAP(2) Bits 31/15 31:16 -- SFR Name CNCON Bits 30/14 -- Bits 29/13 -- Bits 28/12 -- Bits 27/11 -- Bits 26/10 -- Bits 25/9 -- Bits 24/8 -- Bits 23/7 -- Bits 22/6 -- Bits 21/5 -- Bits 20/4 -- Bits 19/3 -- Bits 18/2 -- Bits 17/1 -- Bits 16/0 -- 15:0 ON FRZ SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. CNEN and CNPUE bit(s) are not implemented on 64-pin devices, and read as `0'. All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. TABLE 4-18: SFR Virtual Addr BF88_61D0 BF88_61E0 Legend: Note 1: 2: CHANGE NOTICE AND PULL-UP REGISTERS MAP(2) (CONTINUED) Bits 31/15 31:16 15:0 31:16 -- -- -- -- -- -- -- -- (c) 2009 Microchip Technology Inc. SFR Name CNEN CNPUE Bits 30/14 -- Bits 29/13 -- Bits 28/12 -- Bits 27/11 -- Bits 26/10 -- Bits 25/9 -- Bits 24/8 -- -- Bits 23/7 -- -- Bits 22/6 -- -- Bits 21/5 Bits 20/4 Bits 19/3 Bits 18/2 Bits 17/1 CNEN17 Bits 16/0 CNEN16 CNEN21(1) CNEN20(1) CNEN19(1) CNEN18 CNEN<15:0> CNPUE21(1) CNPUE20(1) CNPUE19(1) CNPUE18 CNPUE17 CNPUE16 15:0 CNPUE<15:0> x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. CNEN and CNPUE bit(s) are not implemented on 64-pin devices, and read as `0'. All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. TABLE 4-19: SFR Virtual Addr BF80_7000 PARALLEL MASTER PORT REGISTERS MAP(1) Bits 31/15 31:16 15:0 31:16 15:0 31:16 31:16 15:0 31:16 15:0 31:16 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ON -- BUSY -- SFR Name PMCON Bits 30/14 -- FRZ -- -- Bits 29/13 -- SIDL -- -- Bits 28/12 -- -- -- Bits 27/11 -- -- -- Bits 26/10 -- PMPTTL -- MODE16 -- Bits 25/9 -- PTWREN -- -- Bits 24/8 -- PTRDEN -- -- Bits 23/7 -- -- -- Bits 22/6 -- -- -- Bits 21/5 -- ALP -- -- Bits 20/4 -- CS2P -- -- Bits 19/3 -- CS1P -- -- Bits 18/2 -- -- -- -- Bits 17/1 -- WRSP -- -- Bits 16/0 -- RDSP -- -- ADRMUX<1:0> INCM<1:0> CSF<1:0> WAITB<1:0> ADDR<13:0> BF80_7010 PMMODE IRQM<1:0> MODE<1:0> WAITM<3:0> WAITE<1:0> Preliminary DS61143F-page 49 BF80_7020 BF80_7030 BF80_7040 BF80_7050 BF80_7060 Legend: Note 1: PMADDR PMDOUT PMDIN PMAEN PMSTAT 15:0 CS2EN/A15 CS1EN/A14 DATAOUT<31:0> DATAIN<31:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PIC32MX3XX/4XX PTEN<15:0> -- 15:0 IBF IBOV -- -- IB3F IB2F IB1F IB0F OBE OBUF -- -- OB3E OB2E OB1E OB0E x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. TABLE 4-20: SFR Virtual Addr BF80_F200 Legend: PROGRAMMING AND DIAGNOSTICS REGISTERS MAP Bits 31/15 31:16 -- SFR Name DDPCON Bits 30/14 -- Bits 29/13 -- Bits 28/12 -- Bits 27/11 -- Bits 26/10 -- Bits 25/9 -- Bits 24/8 -- -- Bits 23/7 -- DDPUSB Bits 22/6 -- DDPU1 Bits 21/5 -- DDPU2 Bits 20/4 -- DDPSPI1 Bits 19/3 -- JTAGEN Bits 18/2 -- TROEN Bits 17/1 -- -- Bits 16/0 -- -- 15:0 -- -- -- -- -- -- -- x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-21: SFR Virtual Addr SFR Name PREFETCH REGISTERS MAP Bits 31/15 31:16 15:0 15:0 31:16 15:0 -- -- DS61143F-page 50 PIC32MX3XX/4XX Bits 30/14 -- -- -- -- -- Bits 29/13 -- -- -- -- -- Bits 28/12 -- -- -- -- -- Bits 27/11 -- -- -- -- -- Bits 26/10 -- -- -- -- -- Bits 25/9 Bits 24/8 Bits 23/7 -- -- -- -- Bits 22/6 -- -- -- -- Bits 21/5 Bits 20/4 Bits 19/3 -- -- -- Bits 18/2 -- Bits 17/1 Bits 16/0 BF88_4000 CHECON(1) BF88_4010 CHEACC(1) -- -- DCSZ<1:0> -- -- -- -- -- -- -- -- PREFEN<1:0> -- -- -- -- -- CHECOH PFMWS<2:0> -- 31:16 CHEWEN -- LTAG BOOT -- -- -- CHEIDX<3:0> LTAG<23:16> LVALID LLOCK -- -- LTYPE -- -- -- -- -- BF88_4020 CHETAG(1) LTAG<15:4> -- -- -- -- -- LMASK<15:5> -- -- -- -- -- -- -- BF88_4030 CHEMSK(1) BF88_4040 BF88_4050 BF88_4060 CHEW0 CHEW1 CHEW2 CHEW3 CHELRU CHEHIT CHEMIS 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 -- -- CHEW0<31:0> CHEW1<31:0> CHEW2<31:0> CHEW3<31:0> -- -- -- -- -- -- -- CHELRU<15:0> CHEHIT<31:0> CHEMIS<31:0> CHELRU<24:16> Preliminary (c) 2009 Microchip Technology Inc. BF88_4070 BF88_4080 BF88_4090 BF88_40A0 BF88_40C0 CHEPFABT Legend: Note 1: 31:16 CHEPFABT<31:0> 15:0 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. This register has corresponding CLR, SET, and INV Registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. TABLE 4-22: SFR Virtual Addr BF80_0200 RTCC REGISTERS MAP(1) Bits 31/15 31:16 -- ON -- SFR Name Bits 30/14 -- FRZ -- Bits 29/13 -- SIDL -- Bits 28/12 -- -- -- Bits 27/11 -- -- -- Bits 26/10 -- -- -- Bits 25/9 Bits 24/8 Bits 23/7 Bits 22/6 Bits 21/5 Bits 20/4 Bits 19/3 Bits 18/2 Bits 17/1 Bits 16/0 CAL<11:0> -- -- -- -- RTSEC SEL -- RTC CLKON -- -- -- -- -- RTCWREN RTCSYNC HALFSEC -- -- -- RTCOE -- RTCCON 15:0 31:16 BF80_0210 RTCALRM Legend: Note 1: ALRM CHIME PIV AMASK<3:0> ARPT<7:0> 15:0 ALRMEN SYNC x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. TABLE 4-22: SFR Virtual Addr BF80_0220 RTCC REGISTERS MAP(1) (CONTINUED) Bits 31/15 31:16 15:0 31:16 15:0 31:16 15:0 31:16 -- (c) 2009 Microchip Technology Inc. SFR Name RTCTIME Bits 30/14 Bits 29/13 Bits 28/12 Bits 27/11 Bits 26/10 Bits 25/9 Bits 24/8 Bits 23/7 Bits 22/6 Bits 21/5 Bits 20/4 Bits 19/3 Bits 18/2 Bits 17/1 Bits 16/0 HR10<3:0> SEC10<3:0> YEAR10<3:0> DAY10<3:0> MIN10<3:0> SEC10<3:0> -- -- -- -- HR01<3:0> SEC01<3:0> YEAR01<3:0> DAY01<3:0> MIN01<3:0> SEC01<3:0> -- -- -- -- -- -- MIN10<3:0> -- -- -- -- -- -- -- -- -- -- -- MONTH10<3:0> MIN10<3:0> MONTH10<3:0> MIN01<3:0> -- -- -- MONTH01<3:0> WDAY01<3:0> MIN01<3:0> -- -- -- MONTH01<3:0> BF80_0230 RTCDATE BF80_0240 ALRMTIME BF80_0250 ALRMDATE Legend: Note 1: 15:0 DAY10<3:0> DAY01<3:0> -- -- -- -- WDAY01<3:0> x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. TABLE 4-23: SFR Virtual Addr SFR Name DEVCFG: DEVICE CONFIGURATION WORD SUMMARY Bits 31/15 31:16 31:16 31:16 -- -- -- Bits 30/14 -- -- -- -- Bits 29/13 -- -- -- -- Bits 28/12 -- -- -- -- Bits 27/11 -- -- -- -- -- -- Bits 26/10 -- -- -- OSC IOFNC -- Bits 25/9 -- -- Bits 24/8 -- -- -- Bits 23/7 -- -- -- FWDTEN IESO -- -- Bits 22/6 -- -- -- -- -- -- Bits 21/5 -- -- FPLLMULT<2:0> -- FSOSCEN -- -- Bits 20/4 -- -- Bits 19/3 -- -- -- Bits 18/2 -- Bits 17/1 -- FPLLODIV<2:0> FPLLIDIV<2:0> Bits 16/0 -- Preliminary DS61143F-page 51 BFC0_2FF0 DEVCFG3 BFC0_2FF4 DEVCFG2 15:0 USERID15 USERID14 USERID13 USERID12 USERID11 USERID10 USERID9 USERID8 USERID7 USERID6 USERID5 USERID4 USERID3 USERID2 USERID1 USERID0 15:0 FUPLLEN(1) FUPLLIDIV<2:0>(1) -- WDTPS<4:0> -- -- -- -- PWP19 ICESEL PWP18 -- FNOSC<2:0> PWP17 PWP16 BFC0_2FF8 DEVCFG1 15:0 31:16 FCKSM<1:0> -- -- FPBDIV<1:0> -- CP POSCMD<1:0> -- BWP -- BFC0_2FFC DEVCFG0 Legend: Note 1: PIC32MX3XX/4XX 15:0 PWP15 PWP14 PWP13 PWP12 -- -- -- x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. These bits are only available on PIC32MX4XX devices. DEBUG<1:0> TABLE 4-24: SFR Virtual Addr BF80_F220 Legend: DEVICE AND REVISION ID SUMMARY Bits 31/15 31:16 SFR Name DEVID Bits 30/14 Bits 29/13 Bits 28/12 Bits 27/11 Bits 26/10 Bits 25/9 Bits 24/8 Bits 23/7 Bits 22/6 Bits 21/5 Bits 20/4 Bits 19/3 Bits 18/2 Bits 17/1 Bits 16/0 VER<3:0> DEVID<15:0> DEVID<27:16> 15:0 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-25: SFR Virtual Addr SFR Name USB REGISTERS MAP Bits 31/15 31:16 15:0 31:16 15:0 31:16 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- DS61143F-page 52 PIC32MX3XX/4XX Bits 30/14 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bits 29/13 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bits 28/12 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bits 27/11 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bits 26/10 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bits 25/9 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bits 24/8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bits 23/7 -- IDIF -- IDIE -- ID -- Bits 22/6 -- -- -- -- -- Bits 21/5 -- -- -- LSTATE -- DPPUL DWN -- -- -- Bits 20/4 -- ACTVIF -- ACTVIE -- -- -- DMPUL DWN -- USLPGRD -- IDLEIF -- IDLEIE -- BTOEF -- BTOEE -- -- USBRST -- -- BDTPTRL<7:1> -- -- -- Bits 19/3 -- -- -- SESVD -- VBUSON -- -- -- TRNIF -- TRNIE -- DFN8EF -- DFN8EE -- DIR -- HOSTEN -- DEVADDR<6:0> -- -- -- -- Bits 18/2 -- -- -- SESEND -- OTGEN -- -- -- SOFIF -- SOFIE -- CRC16EF -- CRC16EE -- PPBI -- RESUME -- -- -- -- Bits 17/1 -- -- -- -- -- -- -- Bits 16/0 -- VBUSVDIF -- VBUSVDIE -- VBUSVD -- BF88_5040 U1OTGIR BF88_5050 BF88_5060 U1OTGIE U1OTG STAT T1MSECIF LSTATEIF T1MSECIE LSTATEIE SESVDIF SESENDIF SESVDIE SESENDIE BF88_5070 U1OTGCON 15:0 31:16 DPPULUP DMPULUP -- UACTPND -- STALLIF -- STALLIE -- BTSEF -- BTSEE -- -- JSTATE -- LSPDEN -- -- -- -- -- -- -- -- -- -- -- VBUSCHG VBUSDIS -- USUS PEND -- UERRIF -- UERRIE -- CRC5EF EOFEF -- CRC5EE EOFEE -- -- -- PPBRST -- -- -- -- FRMH<10:8> -- USBPWR -- URSTIF DETACHIF -- URSTIE DETACHIE -- PIDEF -- PIDEE -- -- -- USBEN SOFEN -- -- -- -- -- BF88_5080 U1PWRC 15:0 31:16 BF88_5200 U1IR 15:0 31:16 RESUME ATTACHIF IF -- -- Preliminary (c) 2009 Microchip Technology Inc. BF88_5210 U1IE 15:0 31:16 RESUME ATTACHIE IE -- BMXEF -- BMXEE -- -- SE0 -- -- DMAEF -- DMAEE -- -- PKTDIS TOKBUSY -- -- -- -- -- BF88_5220 U1EIR 15:0 31:16 BF88_5230 U1EIE 15:0 31:16 15:0 31:16 BF88_5240 U1STAT ENDPT<3:0> BF88_5250 U1CON 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 BF80_5260 U1ADDR BF88_5270 U1BDTP1 BF88_5280 BF88_5290 Legend: U1FRML U1FRMH FRML<7:0> 15:0 -- -- -- -- -- -- -- x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-25: SFR Virtual Addr BF88_52A0 BF88_52B0 USB REGISTERS MAP (CONTINUED) Bits 31/15 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- (c) 2009 Microchip Technology Inc. SFR Name U1TOK U1SOF Bits 30/14 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bits 29/13 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bits 28/12 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bits 27/11 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bits 26/10 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bits 25/9 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bits 24/8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bits 23/7 -- -- -- -- -- UTEYE -- LSPD -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bits 22/6 -- Bits 21/5 -- Bits 20/4 -- -- -- -- -- USBSIDL -- EPCON DIS -- EPCON DIS -- EPCON DIS -- EPCON DIS -- EPCON DIS -- EPCON DIS -- EPCON DIS -- EPCON DIS -- EPCON DIS -- EPCON DIS Bits 19/3 -- -- -- -- -- -- -- EPRXEN -- EPRXEN -- EPRXEN -- EPRXEN -- EPRXEN -- EPRXEN -- EPRXEN -- EPRXEN -- EPRXEN -- EPRXEN Bits 18/2 -- Bits 17/1 -- Bits 16/0 -- -- -- -- -- -- -- EPHSHK -- EPHSHK -- EPHSHK -- EPHSHK -- EPHSHK -- EPHSHK -- EPHSHK -- EPHSHK -- EPHSHK -- EPHSHK PID<3:0> -- -- -- -- UOEMON -- RETRYDIS -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- USBFRZ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CNT<7:0> EP<3:0> -- -- -- -- -- -- EPSTALL -- EPSTALL -- EPSTALL -- EPSTALL -- EPSTALL -- EPSTALL -- EPSTALL -- EPSTALL -- EPSTALL -- EPSTALL BF88_52C0 U1BDTP2 BF88_52D0 U1BDTP3 BF88_52E0 U1CNFG1 BDTPTRH<7:0> BDTPTRU<7:0> BF88_5300 U1EP0 15:0 31:16 EPTXEN -- EPTXEN -- EPTXEN -- EPTXEN -- EPTXEN -- EPTXEN -- EPTXEN -- EPTXEN -- EPTXEN -- EPTXEN BF88_5310 U1EP1 15:0 31:16 Preliminary DS61143F-page 53 BF88_5320 U1EP2 15:0 31:16 BF88_5330 U1EP3 15:0 31:16 BF88_5340 U1EP4 15:0 31:16 PIC32MX3XX/4XX BF88_5350 U1EP5 15:0 31:16 BF88_5360 U1EP6 15:0 31:16 BF88_5370 U1EP7 15:0 31:16 BF88_5380 U1EP8 15:0 31:16 BF88_5390 Legend: U1EP9 15:0 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-25: SFR Virtual Addr BF88_53A0 USB REGISTERS MAP (CONTINUED) Bits 31/15 31:16 -- -- -- -- -- -- -- -- -- -- -- -- DS61143F-page 54 PIC32MX3XX/4XX SFR Name Bits 30/14 -- -- -- -- -- -- -- -- -- -- -- -- Bits 29/13 -- -- -- -- -- -- -- -- -- -- -- -- Bits 28/12 -- -- -- -- -- -- -- -- -- -- -- -- Bits 27/11 -- -- -- -- -- -- -- -- -- -- -- -- Bits 26/10 -- -- -- -- -- -- -- -- -- -- -- -- Bits 25/9 -- -- -- -- -- -- -- -- -- -- -- -- Bits 24/8 -- -- -- -- -- -- -- -- -- -- -- -- Bits 23/7 -- -- -- -- -- -- -- -- -- -- -- -- Bits 22/6 -- -- -- -- -- -- -- -- -- -- -- -- Bits 21/5 -- -- -- -- -- -- -- -- -- -- -- -- Bits 20/4 -- EPCON DIS -- EPCON DIS -- EPCON DIS -- EPCON DIS -- EPCON DIS -- EPCON DIS Bits 19/3 -- EPRXEN -- EPRXEN -- EPRXEN -- EPRXEN -- EPRXEN -- EPRXEN Bits 18/2 -- EPTXEN -- EPTXEN -- EPTXEN -- EPTXEN -- EPTXEN -- EPTXEN Bits 17/1 -- EPSTALL -- EPSTALL -- EPSTALL -- EPSTALL -- EPSTALL -- EPSTALL Bits 16/0 -- EPHSHK -- EPHSHK -- EPHSHK -- EPHSHK -- EPHSHK -- EPHSHK U1EP10 15:0 31:16 BF88_53B0 U1EP11 15:0 31:16 BF88_53C0 U1EP12 15:0 31:16 BF88_53D0 U1EP13 15:0 31:16 BF88_53E0 U1EP14 15:0 31:16 BF88_53F0 Legend: U1EP15 Preliminary (c) 2009 Microchip Technology Inc. 15:0 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. PIC32MX3XX/4XX 5.0 Note: FLASH PROGRAM MEMORY This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" Section 5. "Flash Program Memory" (DS61121) for a detailed description of this peripheral. The manual is available from the Microchip web site (www.Microchip.com/PIC32). PIC32MX3XX/4XX devices contain an internal program Flash memory for executing user code. There are three methods by which the user can program this memory: 1. 2. 3. Run-Time Self Programming (RTSP) In-Circuit Serial ProgrammingTM (ICSPTM) EJTAG Programming RTSP is performed by software executing from either Flash or RAM memory. EJTAG is performed using the EJTAG port of the device and a EJTAG capable programmer. ICSP is performed using a serial data connection to the device and allows much faster programming times than RTSP. RTSP techniques are described in this chapter. The ICSP and EJTAG methods are described in the "PIC32MX3XX/4XX Programming Specification" (DS61145) document, which may be downloaded from the Microchip web site. (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 55 PIC32MX3XX/4XX NOTES: DS61143F-page 56 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX 6.0 Note: RESETS This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" Section 7. "Resets" (DS61118) for a detailed description of this peripheral. The manual is available from the Microchip web site (www.Microchip.com/PIC32). The Reset module combines all Reset sources and controls the device Master Reset signal, SYSRST. The following is a list of device Reset sources: * * * * * * POR: Power-on Reset MCLR: Master Clear Reset Pin SWR: Software Reset WDTR: Watchdog Timer Reset BOR: Brown-out Reset CMR: Configuration Mismatch Reset A simplified block diagram of the Reset module is shown in Figure 6-1. FIGURE 6-1: SYSTEM RESET BLOCK DIAGRAM MCLR Glitch Filter Sleep or Idle Voltage Regulator Enabled VDD WDT Time-out Power-up Timer VDD Rise Detect Brown-out Reset BOR CMR SWR POR SYSRST MCLR WDTR Configuration Mismatch Reset Software Reset (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 57 PIC32MX3XX/4XX NOTES: DS61143F-page 58 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX 7.0 Note: INTERRUPT CONTROLLER This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" Section 8. "Interrupt Controller" (DS61108) for a detailed description of this peripheral. The manual is available from the Microchip web site (www.Microchip.com/PIC32). The PIC32MX3XX/4XX interrupts module includes the following features: * * * * * * * * * * * * Up to 96 interrupt sources Up to 64 interrupt vectors Single and Multi-Vector mode operations 5 external interrupts with edge polarity control Interrupt proximity timer Module Freeze in Debug mode 7 user-selectable priority levels for each vector 4 user-selectable subpriority levels within each priority Dedicated shadow set for highest priority level Software can generate any interrupt User-configurable interrupt vector table location User-configurable interrupt vector spacing PIC32MX3XX/4XX devices generate interrupt requests in response to interrupt events from peripheral modules. The Interrupt Control module exists externally to the CPU logic and prioritizes the interrupt events before presenting them to the CPU. FIGURE 7-1: INTERRUPT CONTROLLER MODULE Interrupt Requests Vector Number Interrupt Controller Priority Level CPU Core Shadow Set Number Note: Several of the registers cited in this section are not in the interrupt controller module. These registers (and bits) are associated with the CPU. Details about them are available in Section 3.0 "PIC32MX MCU". To avoid confusion, a typographic distinction is made for registers in the CPU. The register names in this section, and all other sections of this manual, are signified by uppercase letters only.CPU register names are signified by upper and lowercase letters. For example, INTSTAT is an Interrupts register; whereas, IntCtl is a CPU register. (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 59 PIC32MX3XX/4XX TABLE 7-1: INTERRUPT IRQ AND VECTOR LOCATION IRQ Vector Number Flag 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 23 23 24 24 24 25 25 25 26 27 28 29 30 IFS0<0> IFS0<1> IFS0<2> IFS0<3> IFS0<4> IFS0<5> IFS0<6> IFS0<7> IFS0<8> IFS0<9> IFS0<10> IFS0<11> IFS0<12> IFS0<13> IFS0<14> IFS0<15> IFS0<16> IFS0<17> IFS0<18> IFS0<19> IFS0<20> IFS0<21> IFS0<22> IFS0<23> IFS0<24> IFS0<25> IFS0<26> IFS0<27> IFS0<28> IFS0<29> IFS0<30> IFS0<31> IFS1<0> IFS1<1> IFS1<2> IFS1<3> IFS1<4> Interrupt Bit Location Enable IEC0<0> IEC0<1> IEC0<2> IEC0<3> IEC0<4> IEC0<5> IEC0<6> IEC0<7> IEC0<8> IEC0<9> IEC0<10> IEC0<11> IEC0<12> IEC0<13> IEC0<14> IEC0<15> IEC0<16> IEC0<17> IEC0<18> IEC0<19> IEC0<20> IEC0<21> IEC0<22> IEC0<23> IEC0<24> IEC0<25> IEC0<26> IEC0<27> IEC0<28> IEC0<29> IEC0<30> IEC0<31> IEC1<0> IEC1<1> IEC1<2> IEC1<3> IEC1<4> Priority IPC0<4:2> IPC0<12:10> IPC0<20:18> IPC0<28:26> IPC1<4:2> IPC1<12:10> IPC1<20:18> IPC1<28:26> IPC2<4:2> IPC2<12:10> IPC2<20:18> IPC2<28:26> IPC3<4:2> IPC3<12:10> IPC3<20:18> IPC3<28:26> IPC4<4:2> IPC4<12:10> IPC4<20:18> IPC4<28:26> IPC5<4:2> IPC5<12:10> IPC5<20:18> IPC5<28:26> IPC5<28:26> IPC5<28:26> IPC6<4:2> IPC6<4:2> IPC6<4:2> IPC6<12:10> IPC6<12:10> IPC6<12:10> IPC6<20:18> IPC6<28:26> IPC7<4:2> IPC7<12:10> IPC7<20:18> Subpriority IPC0<1:0> IPC0<9:8> IPC0<17:16> IPC0<25:24> IPC1<1:0> IPC1<9:8> IPC1<17:16> IPC1<25:24> IPC2<1:0> IPC2<9:8> IPC2<17:16> IPC2<25:24> IPC3<1:0> IPC3<9:8> IPC3<17:16> IPC3<25:24> IPC4<1:0> IPC4<9:8> IPC4<17:16> IPC4<25:24> IPC5<1:0> IPC5<9:8> IPC5<17:16> IPC5<25:24> IPC5<25:24> IPC5<25:24> IPC6<1:0> IPC6<1:0> IPC6<1:0> IPC6<9:8> IPC6<9:8> IPC6<9:8> IPC6<17:16> IPC6<25:24> IPC7<1:0> IPC7<9:8> IPC7<17:16> Interrupt Source(1) Highest Natural Order Priority CT - Core Timer Interrupt CS0 - Core Software Interrupt 0 CS1 - Core Software Interrupt 1 INT0 - External Interrupt 0 T1 - Timer1 IC1 - Input Capture 1 OC1 - Output Compare 1 INT1 - External Interrupt 1 T2 - Timer2 IC2 - Input Capture 2 OC2 - Output Compare 2 INT2 - External Interrupt 2 T3 - Timer3 IC3 - Input Capture 3 OC3 - Output Compare 3 INT3 - External Interrupt 3 T4 - Timer4 IC4 - Input Capture 4 OC4 - Output Compare 4 INT4 - External Interrupt 4 T5 - Timer5 IC5 - Input Capture 5 OC5 - Output Compare 5 SPI1E - SPI1 Fault SPI1TX - SPI1 Transfer Done SPI1RX - SPI1 Receive Done U1E - UART1 Error U1RX - UART1 Receiver U1TX - UART1 Transmitter I2C1B - I2C1 Bus Collision Event I2C1S - I2C1 Slave Event I2C1M - I2C1 Master Event CN - Input Change Interrupt AD1 - ADC1 Convert Done PMP - Parallel Master Port CMP1 - Comparator Interrupt CMP2 - Comparator Interrupt Note 1: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Not all interrupt sources are available on all devices. See Table 1: "PIC32MX General Purpose - Features" and Table 2: "PIC32MX USB - Features" for available peripherals. DS61143F-page 60 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX TABLE 7-1: INTERRUPT IRQ AND VECTOR LOCATION (CONTINUED) IRQ Vector Number Flag 31 31 31 32 32 32 33 33 33 34 35 36 37 38 39 44 45 IFS1<5> IFS1<6> IFS1<7> IFS1<8> IFS1<9> IFS1<10> IFS1<11> IFS1<12> IFS1<13> IFS1<14> IFS1<15> IFS1<16> IFS1<17> IFS1<18> IFS1<19> IFS1<24> IFS1<25> Interrupt Bit Location Enable IEC1<5> IEC1<6> IEC1<7> IEC1<8> IEC1<9> IEC1<10> IEC1<11> IEC1<12> IEC1<13> IEC1<14> IEC1<15> IEC1<16> IEC1<17> IEC1<18> IEC1<19> IEC1<24> IEC1<25> Priority IPC7<28:26> IPC7<28:26> IPC7<28:26> IPC8<4:2> IPC8<4:2> IPC8<4:2> IPC8<12:10> IPC8<12:10> IPC8<12:10> IPC8<20:18> IPC8<28:26> IPC9<4:2> IPC9<12:10> IPC9<20:18> IPC9<28:26> IPC11<4:2> IPC11<12:10> Subpriority IPC7<25:24> IPC7<25:24> IPC7<25:24> IPC8<1:0> IPC8<1:0> IPC8<1:0> IPC8<9:8> IPC8<9:8> IPC8<9:8> IPC8<17:16> IPC8<25:24> IPC9<1:0> IPC9<9:8> IPC9<17:16> IPC9<25:24> IPC11<1:0> IPC11<9:8> Interrupt Source(1) Highest Natural Order Priority SPI2E - SPI2 Fault SPI2TX - SPI2 Transfer Done SPI2RX - SPI2 Receive Done U2E - UART2 Error U2RX - UART2 Receiver U2TX - UART2 Transmitter I2C2B - I2C2 Bus Collision Event I2C2S - I2C2 Slave Event I2C2M - I2C2 Master Event FSCM - Fail-Safe Clock Monitor RTCC - Real-Time Clock DMA0 - DMA Channel 0 DMA1 - DMA Channel 1 DMA2 - DMA Channel 2 DMA3 - DMA Channel 3 FCE - Flash Control Event USB (Reserved) Lowest Natural Order Priority Note 1: 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 56 57 Not all interrupt sources are available on all devices. See Table 1: "PIC32MX General Purpose - Features" and Table 2: "PIC32MX USB - Features" for available peripherals. (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 61 PIC32MX3XX/4XX NOTES: DS61143F-page 62 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX 8.0 Note: OSCILLATOR CONFIGURATION This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" Section 6. "Oscillator Configuration" (DS61112) for a detailed description of this peripheral. The manual is available from the Microchip web site (www.Microchip.com/PIC32). The PIC32MX oscillator system has the following modules and features: * A total of four external and internal oscillator options as clock sources * On-chip PLL (phase-locked loop) with userselectable input divider, multiplier, and output divider to boost operating frequency on select internal and external oscillator sources * On-chip user-selectable divisor postscaler on select oscillator sources * Software-controllable switching between various clock sources * A Fail-Safe Clock Monitor (FSCM) that detects clock failure and permits safe application recovery or shutdown * Dedicated on-chip PLL for USB peripheral (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 63 PIC32MX3XX/4XX FIGURE 8-1: PIC32MX3XX/4XX FAMILY CLOCK DIAGRAM USB PLL UFIN USB Clock (48 MHz) PLL x24 div 2 UFRCEN FUPLLEN XT, HS, EC 4 MHz FIN 5 MHz XTPLL, HSPLL, FIN ECPLL, FRCPLL div x div y PLL PLL Input Divider FPLLIDIV<2:0> COSC<2:0> PLL Output Divider PLLODIV<2:0> Postscaler Peripherals div x PBCLK div x Primary Oscillator POSC RF(2) XTAL RS (1) UFIN = 4 MHz FUPLLDIV<2:0> C1(3) OSC1 To Internal Logic Enable C2(3) OSC2(4) FRC Oscillator 8 MHz typical TUN<5:0> PBDIV<2:0> PLL Multiplier PLLMULT<2:0> FRC FRC /16 FRCDIV CPU and Select Peripherals div 16 Postscaler FRCDIV<2:0> LPRC Oscillator 31.25 kHz typical LPRC Secondary Oscillator (SOSC) SOSCO 32.768 kHz SOSCEN and FSOSCEN Clock Control Logic SOSCI Fail-Safe Clock Monitor FSCM INT FSCM Event SOSC NOSC<2:0> COSC<2:0> OSWEN FSCMEN<1:0> WDT, PWRT Timer1, RTCC Notes: 1. A series resistor, RS, may be required for AT strip cut crystals. 2. The internal feedback resistor, RF, is typically in the range of 2 to 10 M. 3. Refer to the "PIC32MX Family Reference Manual" Section 6. "Oscillator Configuration" (DS61112) for help determining the best oscillator components. 4. PBCLK out is available on the OSC2 pin in certain clock modes. DS61143F-page 64 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX 9.0 Note: PREFETCH CACHE This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" Section 4. "Prefetch Cache" (DS61119) for a detailed description of this peripheral. The manual is available from the Microchip web site (www.Microchip.com/PIC32). 9.1 * * * * * * * * Features Prefetch cache increases performance for applications executing out of the cacheable program flash memory regions by implementing instruction caching, constant data caching, and instruction prefetching. 16 Fully Associative Lockable Cache Lines 16-byte Cache Lines Up to 4 Cache Lines Allocated to Data 2 Cache Lines with Address Mask to hold repeated instructions Pseudo LRU replacement policy All Cache Lines are software writable 16-byte parallel memory fetch Predictive Instruction Prefetch FIGURE 9-1: PREFETCH MODULE BLOCK DIAGRAM FSM BMX/CPU CTRL Tag Logic Cache Line CTRL Bus Ctrl Cache Ctrl Prefetch Ctrl Hit LRU Miss LRU Hit Logic PreFetch Pre-Fetch Tag CTRL PreFetch Pre-Fetch RDATA Cache Line Address Encode BMX/CPU RDATA PFM (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 65 PIC32MX3XX/4XX NOTES: DS61143F-page 66 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX 10.0 Note: DIRECT MEMORY ACCESS (DMA) CONTROLLER This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" Section 31. "Direct Memory Access (DMA) Controller" (DS61117) for a detailed description of this peripheral. The manual is available from the Microchip web site (www.Microchip.com/PIC32). The PIC32MX Direct Memory Access (DMA) controller is a bus master module useful for data transfers between different devices without CPU intervention. The source and destination of a DMA transfer can be any of the memory mapped modules existent in the PIC32MX (such as Peripheral Bus (PBUS) devices: SPI, UART, I2CTM, etc.) or memory itself. Following are some of the key features of the DMA controller module: * Four Identical Channels, each featuring: - Auto-Increment Source and Destination Address Registers - Source and Destination Pointers - Memory to Memory and Memory to Peripheral Transfers * Automatic Word-Size Detection: - Transfer Granularity, down to byte level - Bytes need not be word-aligned at source and destination * Fixed Priority Channel Arbitration * Flexible DMA Channel Operating Modes: - Manual (software) or automatic (interrupt) DMA requests - One-Shot or Auto-Repeat Block Transfer modes - Channel-to-channel chaining * Flexible DMA Requests: - A DMA request can be selected from any of the peripheral interrupt sources - Each channel can select any (appropriate) observable interrupt as its DMA request source - A DMA transfer abort can be selected from any of the peripheral interrupt sources - Pattern (data) match transfer termination * Multiple DMA Channel Status Interrupts: - DMA channel block transfer complete - Source empty or half empty - Destination full or half-full - DMA transfer aborted due to an external event - Invalid DMA address generated * DMA Debug Support Features: - Most recent address accessed by a DMA channel - Most recent DMA channel to transfer data * CRC Generation Module: - CRC module can be assigned to any of the available channels - CRC module is highly configurable FIGURE 10-1: INT Controller DMA BLOCK DIAGRAM System IRQ Peripheral Bus Address Decoder Channel 0 Control I0 SE L Channel 1 Control I1 I2 Y Bus Interface Device Bus + Bus Arbitration Global Control (DMACON) Channel n Control In L SE Channel Priority Arbitration (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 67 PIC32MX3XX/4XX NOTES: DS61143F-page 68 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX 11.0 Note: USB ON-THE-GO (OTG) This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" Section 27. "USB On-The-Go (OTG)" (DS61126) for a detailed description of this peripheral. The manual is available from the Microchip web site (www.Microchip.com/PIC32). The PIC32MX USB module includes the following features: * * * * * * * * * USB Full-Speed Support for Host and Device Low-Speed Host Support USB OTG Support Integrated Signaling Resistors Integrated Analog Comparators for VBUS Monitoring Integrated USB Transceiver Transaction Handshaking Performed by Hardware Endpoint Buffering Anywhere in System RAM Integrated DMA to Access System RAM and Flash Note: IMPORTANT: The implementation and use of the USB specifications, as well as other third-party specifications or technologies, may require licensing; including, but not limited to, USB Implementers Forum, Inc. (also referred to as USB-IF). The user is fully responsible for investigating and satisfying any applicable licensing obligations. The Universal Serial Bus (USB) module contains analog and digital components to provide a USB 2.0 fullspeed and low-speed embedded host, full-speed device, or OTG implementation with a minimum of external components. This module in Host mode is intended for use as an embedded host and therefore does not implement a UHCI or OHCI controller. The USB module consists of the clock generator, the USB voltage comparators, the transceiver, the Serial Interface Engine (SIE), a dedicated USB DMA controller, pull-up and pull-down resistors, and the register interface. A block diagram of the PIC32MX USB OTG module is presented in Figure 11-1. The clock generator provides the 48 MHz clock required for USB full-speed and low-speed communication. The voltage comparators monitor the voltage on the VBUS pin to determine the state of the bus. The transceiver provides the analog translation between the USB bus and the digital logic. The SIE is a state machine that transfers data to and from the endpoint buffers, and generates the hardware protocol for data transfers. The USB DMA controller transfers data between the data buffers in RAM and the SIE. The integrated pull-up and pull-down resistors eliminate the need for external signaling components. The register interface allows the CPU to configure and communicate with the module. (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 69 PIC32MX3XX/4XX FIGURE 11-1: PIC32MX3XX/4XX FAMILY USB INTERFACE DIAGRAM USBEN USB Suspend CPU Clock Not POSC Sleep Primary Oscillator (POSC) Div x OSC1 FRC Oscillator 8 MHz Typical TUN<5:0>(4) UFIN(5) PLL Div 2 FUPLLEN(6) UFRCEN(3) FUPLLIDIV(6) USB Suspend Sleep or Idle To Clock Generator for Core and Peripherals OSC2 (PB out)(1) USB Module SRP Charge SRP Discharge USB Voltage Comparators 48 MHz USB Clock(7) VBUS Full Speed Pull-up D+(2) Host Pull-down Transceiver Registers and Control Interface SIE Low Speed Pull-up D-(2) DMA Host Pull-down System RAM ID Pull-up ID(8) VBUSON(8) VUSB Transceiver Power 3.3V Note 1: 2: 3: 4: 5: 6: 7: 8: PB clock is only available on this pin for select EC modes. Pins can be used as digital inputs when USB is not enabled. This bit field is contained in the OSCCON register. This bit field is contained in the OSCTRM register. USB PLL UFIN requirements: 4 MHz. This bit field is contained in the DEVCFG2 register. A 48 MHz clock is required for proper USB operation. Pins can be used as GPIO when the USB module is disabled. DS61143F-page 70 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX 12.0 Note: I/O PORTS This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" Section 12. "I/O Ports" (DS61120) for a detailed description of this peripheral. The manual is available from the Microchip web site (www.Microchip.com/PIC32). These functions depend on which peripheral features are on the device. In general, when a peripheral is functioning, that pin may not be used as a general purpose I/O pin. Following are some of the key features of this module: * Individual output pin open-drain enable/disable * Individual input pin weak pull-up enable/disable * Monitor selective inputs and generate interrupt when change in pin state is detected * Operation during CPU Sleep and Idle modes * Fast bit manipulation using CLR, SET and INV registers Figure 12-1 shows a block diagram of a typical multiplexed I/O port. General purpose I/O pins are the simplest of peripherals. They allow the PIC(R) MCU to monitor and control other devices. To add flexibility and functionality, some pins are multiplexed with alternate function(s). FIGURE 12-1: BLOCK DIAGRAM OF A TYPICAL MULTIPLEXED PORT STRUCTURE Peripheral Module Peripheral Module Enable Peripheral Output Enable Peripheral Output Data PIO Module RD ODC Data Bus SYSCLK WR ODC RD TRIS D Q ODC CK EN Q 1 0 0 1 IO Cell D Q 1 0 TRIS CK EN Q WR TRIS D Q Output Multiplexers LAT CK Q EN IO Pin WR LAT WR PORT RD LAT 1 RD PORT 0 Q Q D CK Q Q D CK Sleep SYSCLK Synchronization Peripheral Input Peripheral Input Buffer R Legend: R = Peripheral input buffer types may vary. Refer to Table 1-1 for more information. Note: This block diagram is a general representation of a shared port/peripheral structure for illustration purposes only. The actual structure for any specific port/peripheral combination may be different than it is shown here. (c) 2009 Microchip Technology Inc. Preliminary DS61143F - page 71 PIC32MX3XX/4XX 12.1 Parallel I/O (PIO) Ports 12.1.2 DIGITAL INPUTS All port pins have three registers (TRIS, LAT, and PORT) that are directly associated with their operation. TRIS is a data direction or tri-state control register that determines whether a digital pin is an input or an output. Setting a TRISx register bit = 1 configures the corresponding I/O pin as an input; setting a TRISx register bit = 0 configures the corresponding I/O pin as an output. All port I/O pins are defined as inputs after a device Reset. Certain I/O pins are shared with analog peripherals and default to analog inputs after a device Reset. PORT is a register used to read the current state of the signal applied to the port I/O pins. Writing to a PORTx register performs a write to the port's latch, LATx register, latching the data to the port's I/O pins. LAT is a register used to write data to the port I/O pins. The LATx latch register holds the data written to either the LATx or PORTx registers. Reading the LATx latch register reads the last value written to the corresponding port or latch register. Not all port I/O pins are implemented on some devices, therefore, the corresponding PORTx, LATx and TRISx register bits will read as zeros. Pins are configured as digital inputs by setting the corresponding TRIS register bits = 1. When configured as inputs, they are either TTL buffers or Schmitt Triggers. Several digital pins share functionality with analog inputs and default to the analog inputs at POR. Setting the corresponding bit in the AD1PCFG register = 1 enables the pin as a digital pin. Digital only pins are capable of input voltages up to 5.5V. Any pin that shares digital and analog functionality is limited to voltages up to VDD + 0.3V. . TABLE 12-1: MAXIMUM INPUT PIN VOLTAGES VIH (max) Input Pin Mode(s) Digital Only Digital + Analog Analog VIH = 5.5v VIH = VDD + 0.03v VIH = VDD + 0.03v Note: Refer to Section 28.0 "Electrical Characteristics" regarding the VIH specification. Note: 12.1.1 CLR, SET AND INV REGISTERS 12.1.3 Analog levels on any pin that is defined as a digital input (including the ANx pins) may cause the input buffer to consume current that exceeds the device specifications. Every I/O module register has a corresponding CLR (clear), SET (set) and INV (invert) register designed to provide fast atomic bit manipulations. As the name of the register implies, a value written to a SET, CLR or INV register effectively performs the implied operation, but only on the corresponding base register and only bits specified as `1' are modified. Bits specified as `0' are not modified. Reading SET, CLR and INV registers returns undefined values. To see the affects of a write operation to a SET, CLR or INV register, the base register must be read. To set PORTC bit 0, write to the LATSET register: LATCSET = 0x0001; ANALOG INPUTS Certain pins can be configured as analog inputs used by the ADC and Comparator modules. Setting the corresponding bits in the AD1PCFG register = 0 enables the pin as an analog input pin and must have the corresponding TRIS bit set = 1 (input). If the TRIS bit is cleared = 0 (output), the digital output level (VOH or VOL) will be converted. Any time a port I/O pin is configured as analog, its digital input is disabled and the corresponding PORTx register bit will read `0'. The AD1PCFG Register has a default value of 0x0000; therefore, all pins that share ANx functions are analog (not digital) by default. To clear PORTC bit 0, write to the LATCLR register: LATCCLR = 0x0001; 12.1.4 DIGITAL OUTPUTS To toggle PORTC bit 0, write to the LATINV register: LATCINV = 0x0001; Note: Using a PORTxINV register to toggle a bit is recommended because the operation is performed in hardware atomically, using fewer instructions as compared to the traditional read-modify-write method shown below: PORTC ^= 0x0001; Pins are configured as digital outputs by setting the corresponding TRIS register bits = 0. When configured as digital outputs, these pins are CMOS drivers or can be configured as open drain outputs by setting the corresponding bits in the ODCx Open-Drain Configuration register. Digital output pin voltage is limited to VDD. 12.1.5 ANALOG OUTPUTS Certain pins can be configured as analog outputs, such as the CVREF output voltage used by the comparator module. Configuring the Comparator Reference module to provide this output will present the analog output voltage on the pin, independent of the TRIS register setting for the corresponding pin. DS61143F - page 72 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX 13.0 Note: TIMER1 This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" Section 14. "Timers" (DS61105) for a detailed description of this peripheral. The manual is available from the Microchip web site (www.Microchip.com/PIC32). 13.1 Additional Supported Features * Selectable clock prescaler * Timer operation during CPU Idle and Sleep mode * Fast bit manipulation using CLR, SET and INV registers * Asynchronous mode can be used with the SOSC to function as a Real-Time Clock (RTC). This family of PIC32MX devices features one synchronous/asynchronous 16-bit timer that can operate as a free-running interval timer for various timing applications and counting external events. This timer can also be used with the Low-Power Secondary Oscillator (SOSC) for real-time clock applications. The following modes are supported: * * * * Synchronous Internal Timer Synchronous Internal Gated Timer Synchronous External Timer Asynchronous External Timer FIGURE 13-1: TIMER1 BLOCK DIAGRAM(1) PR1 Equal 16-bit Comparator TSYNC (T1CON<2>) 1 Sync Reset T1IF Event Flag 0 1 TGATE (T1CON<7>) TMR1 0 Q Q D TGATE (T1CON<7>) TCS (T1CON<1>) ON (T1CON<15>) SOSCO/T1CK SOSCEN SOSCI Gate Sync PBCLK x1 10 00 Prescaler 1, 8, 64, 256 2 TCKPS<1:0> (T1CON<5:4>) Note 1: The default state of the SOSCEN (OSCCON<1>) during a device Reset is controlled by the FSOSCEN bit in Configuration Word DEVCFG1. (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 73 PIC32MX3XX/4XX NOTES: DS61143F-page 74 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX 14.0 Note: TIMERS 2, 3, 4, 5 This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" Section 14. "Timers" (DS61105) for a detailed description of this peripheral. The manual is available from the Microchip web site (www.Microchip.com/PIC32). Note: Throughout this chapter, references to registers TxCON, TMRx, and PRx use `x' to represent Timer2 through 5 in 16-bit modes. In 32-bit modes, `x' represents Timer2 or 4; `y' represents Timer3 or 5. 14.1 Additional Supported Features This family of PIC32MX devices features four synchronous 16-bit timers (default) that can operate as a free-running interval timer for various timing applications and counting external events. The following modes are supported: * Synchronous Internal 16-bit Timer * Synchronous Internal 16-bit Gated Timer * Synchronous External 16-bit Timer Two 32-bit synchronous timers are available by combining Timer2 with Timer3 and Timer4 with Timer5. The 32-bit timers can operate in three modes: * Synchronous Internal 32-bit Timer * Synchronous Internal 32-bit Gated Timer * Synchronous External 32-bit Timer * Selectable clock prescaler * Timers operational during CPU Idle * Time base for input capture and output compare modules (Timer2 and Timer3 only) * ADC event trigger (Timer3 only) * Fast bit manipulation using CLR, SET and INV registers FIGURE 14-1: TIMER2, 3, 4, 5 BLOCK DIAGRAM (16-BIT) TMRx Sync ADC Event Trigger(1) Equal Comparator x 16 PRx Reset TxIF Event Flag 0 1 TGATE (TxCON<7>) Q Q D TGATE (TxCON<7>) TCS (TxCON<1>) ON (TxCON<15>) TxCK(2) Gate Sync PBCLK x1 10 00 Prescaler 1, 2, 4, 8, 16, 32, 64, 256 3 TCKPS (TxCON<6:4>) Note 1: ADC event trigger is available on Timer3 only. 2: TxCK pins not available on 64-pin devices. (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 75 PIC32MX3XX/4XX FIGURE 14-2: TIMER2/3, 4/5 BLOCK DIAGRAM (32-BIT) Reset TMRy MSHalfWord ADC Event Trigger(3) Equal TMRx LSHalfWord Sync 32-bit Comparator PRy TyIF Event Flag 0 1 TGATE (TxCON<7>) PRx Q Q D TGATE (TxCON<7>) TCS (TxCON<1>) ON (TxCON<15>) TxCK(2) Gate Sync PBCLK x1 10 00 Prescaler 1, 2, 4, 8, 16, 32, 64, 256 3 TCKPS (TxCON<6:4>) Note 1: In this diagram, the use of "x' in registers TxCON, TMRx, PRx, TxCK refers to either Timer2 or Timer4; the use of `y' in registers TyCON, TMRy, PRy, TyIF refers to either Timer3 or Timer5. 2: TxCK pins not available on 64-pin devices. 3: ADC event trigger is available only on Timer2/3 pair. DS61143F-page 76 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX 15.0 Note: INPUT CAPTURE This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" Section 15. "Input Capture" (DS61122) for a detailed description of this peripheral. The manual is available from the Microchip web site (www.Microchip.com/PIC32). 2. Capture timer value on every edge (rising and falling) 3. Capture timer value on every edge (rising and falling), specified edge first. 4. Prescaler Capture Event modes - Capture timer value on every 4th rising edge of input at ICx pin - Capture timer value on every 16th rising edge of input at ICx pin Each input capture channel can select between one of two 16-bit timers (Timer2 or Timer3) for the time base, or two 16-bit timers (Timer2 and Timer3) together to form a 32-bit timer. The selected timer can use either an internal or external clock. Other operational features include: * Device wake-up from capture pin during CPU Sleep and Idle modes * Interrupt on input capture event * 4-word FIFO buffer for capture values - Interrupt optionally generated after 1, 2, 3 or 4 buffer locations are filled * Input capture can also be used to provide additional sources of external interrupts The Input Capture module is useful in applications requiring frequency (period) and pulse measurement. The PIC32MX3XX/4XX devices support up to five input capture channels. The input capture module captures the 16-bit or 32-bit value of the selected Time Base registers when an event occurs at the ICx pin. The events that cause a capture event are listed below in three categories: 1. Simple Capture Event modes - Capture timer value on every falling edge of input at ICx pin - Capture timer value on every rising edge of input at ICx pin FIGURE 15-1: ICx Input INPUT CAPTURE BLOCK DIAGRAM Timer 3 Timer 2 ICTMR 0 ICC32 FIFO Control ICxBUF<31:16> Prescaler 1, 4, 16 Edge Detect ICxBUF<15:0> 1 ICM<2:0> ICFEDGE ICM<2:0> ICxCON ICBNE ICOV Interrupt Event Generation Data Space Interface ICI<1:0> Interrupt Peripheral Data Bus (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 77 PIC32MX3XX/4XX NOTES: DS61143F-page 78 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX 16.0 Note: OUTPUT COMPARE This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" Section 16. "Output Capture" (DS61111) for a detailed description of this peripheral. The manual is available from the Microchip web site (www.Microchip.com/PIC32). The following are some of the key features: * Multiple output compare modules in a device * Programmable interrupt generation on compare event * Single and Dual Compare modes * Single and continuous output pulse generation * Pulse-Width Modulation (PWM) mode * Hardware-based PWM Fault detection and automatic output disable * Programmable selection of 16-bit or 32-bit time bases. * Can operate from either of two available 16-bit time bases or a single 32-bit time base. The Output Compare module (OCMP) is used to generate a single pulse or a train of pulses in response to selected time base events. For all modes of operation, the OCMP module compares the values stored in the OCxR and/or the OCxRS registers to the value in the selected timer. When a match occurs, the OCMP module generates an event based on the selected mode of operation. FIGURE 16-1: OUTPUT COMPARE MODULE BLOCK DIAGRAM Set Flag bit OCxIF(1) OCxRS(1) OCxR(1) Output Logic 3 OCM<2:0> Mode Select S R Q OCx(1) Output Enable OCFA or OCFB (see Note 2) Comparator 0 1 OCTSEL 0 1 16 16 TMR register inputs from time bases (see Note 3). Period match signals from time bases (see Note 3). Note 1: Where `x' is shown, reference is made to the registers associated with the respective output compare channels 1 through 5. 2: The OCFA pin controls the OC1-OC4 channels. The OCFB pin controls the OC5 channel. 3: Each output compare channel can use one of two selectable 16-bit time bases or a single 32-bit timer base. (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 79 PIC32MX3XX/4XX NOTES: DS61143F-page 80 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX 17.0 Note: SERIAL PERIPHERAL INTERFACE (SPI) This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" Section 23. "Serial Peripheral Interface (SPI)" (DS61106) for a detailed description of this peripheral. The manual is available from the Microchip web site (www.Microchip.com/PIC32). Following are some of the key features of this module: * * * * * * * * Master and Slave Modes Support Four Different Clock Formats Framed SPI Protocol Support User Configurable 8-bit, 16-bit and 32-bit Data Width Separate SPI Data Registers for Receive and Transmit Programmable Interrupt Event on every 8-bit, 16-bit and 32-bit Data Transfer Operation during CPU Sleep and Idle Mode Fast Bit Manipulation using CLR, SET and INV Registers The SPI module is a synchronous serial interface useful for communicating with external peripherals and other microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc. The PIC32MX SPI module is compatible with Motorola(R) SPI and SIOP interfaces. FIGURE 17-1: SPI MODULE BLOCK DIAGRAM Internal Data Bus SPIxBUF Read Write Registers share address SPIxBUF SPIxRXB SPIxTXB Transmit Receive SPIxSR SDIx SDOx Slave Select and Frame Sync Control bit 0 Shift Control Clock Control Edge Select Baud Rate Generator SCKx Enable Master Clock Note: Access SPIxTXB and SPIxRXB registers via SPIxBUF register. SSx/FSYNC PBCLK (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 81 PIC32MX3XX/4XX NOTES: DS61143F-page 82 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX 18.0 Note: INTER-INTEGRATED CIRCUIT (I2CTM) This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" Section 24. "Inter-Integrated Circuit (I2C)" (DS61116) for a detailed description of this peripheral. The manual is available from the Microchip web site (www.Microchip.com/PIC32). The I2C module provides complete hardware support for both Slave and Multi-Master modes of the I2C serial communication standard. Figure 18-1 shows the I2C module block diagram. The PIC32MX3XX/4XX devices have up to two I2C interface modules, denoted as I2C1 and I2C2. Each I2C module has a 2-pin interface: the SCLx pin is clock and the SDAx pin is data. Each I2C module `I2Cx' (x = 1 or 2) offers the following key features: * I2C Interface Supporting both Master and Slave Operation. * I2C Slave Mode Supports 7 and 10-bit Address. * I2C Master Mode Supports 7 and 10-bit Address. * I2C Port allows Bidirectional Transfers between Master and Slaves. * Serial Clock Synchronization for I2C Port can be used as a Handshake Mechanism to Suspend and Resume Serial Transfer (SCLREL control). * I2C Supports Multi-master Operation; Detects Bus Collision and Arbitrates Accordingly. * Provides Support for Address Bit Masking. (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 83 PIC32MX3XX/4XX FIGURE 18-1: I2CTM BLOCK DIAGRAM (X = 1 OR 2) Internal Data Bus I2CxRCV Shift Clock I2CxRSR LSB SDAx Address Match Read SCLx Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop Bit Detect Start and Stop Bit Generation Control Logic Write I2CxSTAT Read Write I2CxCON Read Collision Detect Acknowledge Generation Clock Stretching Write I2CxTRN LSB Shift Clock Reload Control Read Write I2CxBRG Read BRG Down Counter PBCLK DS61143F-page 84 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX 19.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" Section 21. "Universal Asynchronous Receiver Transmitter (UART)" (DS61107) for a detailed description of this peripheral. The manual is available from the Microchip web site (www.Microchip.com/PIC32). The primary features of the UART module are: * * * * * * * * * * * * * Full-duplex, 8-bit or 9-bit data transmission Even, odd or no parity options (for 8-bit data) One or two Stop bits Hardware auto-baud feature Hardware flow control option Fully integrated Baud Rate Generator (BRG) with 16-bit prescaler Baud rates ranging from 76 bps to 20 Mbps at 80 MHz 4-level-deep First-In-First-Out (FIFO) Transmit Data Buffer 4-level-deep FIFO Receive Data Buffer Parity, framing and buffer overrun error detection Support for interrupt only on address detect (9th bit = 1) Separate transmit and receive interrupts Loopback mode for diagnostic support Note: The UART module is one of the serial I/O modules available in PIC32MX3XX/4XX family devices. The UART is a full-duplex, asynchronous communication channel that communicates with peripheral devices and personal computers through protocols such as RS232, RS-485, LIN 1.2 and IrDA(R). The module also supports the hardware flow control option, with UxCTS and UxRTS pins, and also includes an IrDA encoder and decoder. * LIN 1.2 protocol support * IrDA encoder and decoder with 16x baud clock output for external IrDA encoder/decoder support Figure 19-1 shows a simplified block diagram of the UART. FIGURE 19-1: UART SIMPLIFIED BLOCK DIAGRAM Baud Rate Generator IrDA(R) BCLKx Hardware Flow Control UxRTS UxCTS UARTx Receiver UxRX UARTx Transmitter UxTX (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 85 PIC32MX3XX/4XX FIGURE 19-2: TRANSMISSION (8-BIT OR 9-BIT DATA) Write to UxTXREG BCLK/16 (Shift Clock) UxTX Character 1 Start bit bit 0 bit 1 Character 1 bit 7/8 Stop bit UxTXIF Character 1 to Transmit Shift Register TRMT bit UxTXIF Cleared by User FIGURE 19-3: TWO CONSECUTIVE TRANSMISSIONS Write to UxTXREG BCLK/16 (Shift Clock) UxTX Character 1 Character 2 Start bit bit 0 bit 1 Character 1 bit 7/8 Stop bit Start bit bit 0 Character 2 UxTXIF (UTXISEL0 = 0) UxTXIF (UTXISEL0 = 1) UxTXIF Cleared by User in Software TRMT bit Character 1 to Transmit Shift Register Character 2 to Transmit Shift Register DS61143F-page 86 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX FIGURE 19-4: UxRX UxRXIF (RXISEL = 0x) Character 1 to UxRXREG RIDLE bit Character 2 to UxRXREG UART RECEPTION Start bit bit 0 Start bit bit 0 bit1 bit 7 Stop bit bit 7 Stop bit Note: This timing diagram shows 2 characters received on the UxRX input. FIGURE 19-5: UART RECEPTION WITH RECEIVE OVERRUN Character 1 Characters 2, 3, 4, 5 bit 7/8 Stop bit Start bit bit 0 bit 7/8 Stop bit Character 6 Start bit bit 7/8 Stop bit UxRX Start bit bit 0 bit 1 Character 1, 2, 3, 4 Stored in Receive FIFO OERR bit Character 5 Held in UxRSR OERR Cleared by User RIDLE bit Note: This diagram shows 6 characters received without the user reading the input buffer. The 5th character received is held in the Receive Shift register. An overrun error occurs at the start of the 6th character. (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 87 PIC32MX3XX/4XX NOTES: DS61143F-page 88 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX 20.0 Note: PARALLEL MASTER PORT (PMP) This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" Section 13. "Parallel Master Port (PMP)" (DS61128) for a detailed description of this peripheral. The manual is available from the Microchip web site (www.Microchip.com/PIC32). Key features of the PMP module include: * * * * 8-bit,16-bit interface Up to 16 programmable address lines Up to two Chip Select lines Programmable strobe options - Individual read and write strobes, or - Read/write strobe with enable strobe Address auto-increment/auto-decrement Programmable address/data multiplexing Programmable polarity on control signals Parallel Slave Port support - Legacy addressable - Address support - 4-byte deep auto-incrementing buffer Programmable Wait states Operate during CPU Sleep and Idle modes Fast bit manipulation using CLR, SET and INV registers Freeze option for in-circuit debugging Note: The PMP is a parallel 8-bit/16-bit input/output module specifically designed to communicate with a wide variety of parallel devices, such as communications peripherals, LCDs, external memory devices, and microcontrollers. Because the interface to parallel peripherals varies significantly, the PMP module is highly configurable. * * * * * * * * On 64-pin devices, data pins PMD<15:8> are not available. FIGURE 20-1: PMP MODULE PINOUT AND CONNECTIONS TO EXTERNAL DEVICES Address Bus Data Bus Control Lines PIC32MX3XX/4XX Parallel Master Port PMA<0> PMALL PMA<1> PMALH Up to 16-bit Address PMA<13:2> PMA<14> PMCS1 PMA<15> PMCS2 FLASH EEPROM SRAM PMRD PMRD/PMWR PMWR PMENB Microcontroller LCD FIFO buffer PMD<7:0> PMD<15:8>(1) 16/8-bit Data (with or without multiplexed addressing) Note 1: On 64-pin devices, data pins PMD<15:8> are not available in 16-bit Master modes (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 89 PIC32MX3XX/4XX NOTES: DS61143F-page 90 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX 21.0 Note: REAL-TIME CLOCK AND CALENDAR (RTCC) This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" Section 29. "Real-Time Clock and Calendar (RTCC)" (DS61125) for a detailed description of this peripheral. The manual is available from the Microchip web site (www.Microchip.com/PIC32). Following are some of the key features of this module: * * * * * Time: Hours, Minutes and Seconds 24-Hour Format (Military Time) Visibility of One-Half-Second Period Provides Calendar: Weekday, Date, Month and Year Alarm Intervals are configurable for Half of a Second, One Second, 10 Seconds, One Minute, 10 Minutes, One Hour, One Day, One Week, One Month and One Year Alarm Repeat with Decrementing Counter Alarm with Indefinite Repeat: Chime Year Range: 2000 to 2099 Leap Year Correction BCD Format for Smaller Firmware Overhead Optimized for Long-Term Battery Operation Fractional Second Synchronization User Calibration of the Clock Crystal Frequency with Auto-Adjust Calibration Range: 0.66 Seconds Error per Month Calibrates up to 260 ppm of Crystal Error Requirements: External 32.768 kHz Clock Crystal Alarm Pulse or Seconds Clock Output on RTCC pin The PIC32MX RTCC module is intended for applications in which accurate time must be maintained for extended periods of time with minimal or no CPU intervention. Low-power optimization provides extended battery lifetime while keeping track of time. * * * * * * * * * * * * FIGURE 21-1: 32.768 kHz Input from Secondary Oscillator (SOSC) RTCC BLOCK DIAGRAM RTCC Prescalers 0.5s RTCC Timer Alarm Event RTCVAL YEAR, MTH, DAY WKDAY HR, MIN, SEC Comparator MTH, DAY Compare Registers with Masks Repeat Counter ALRMVAL WKDAY HR, MIN, SEC RTCC Interrupt RTCC Interrupt Logic Alarm Pulse Seconds Pulse RTCC Pin RTCOE (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 91 PIC32MX3XX/4XX NOTES: DS61143F-page 92 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX 22.0 Note: 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" Section 17. "10-bit Analog-to-Digital Converter (ADC)" (DS61104) for a detailed description of this peripheral. The manual is available from the Microchip web site (www.Microchip.com/PIC32). A block diagram of the 10-bit ADC is shown in Figure 22-1. The 10-bit ADC has 16 analog input pins, designated AN0-AN15. In addition, there are two analog input pins for external voltage reference connections. These voltage reference inputs may be shared with other analog input pins and may be common to other analog module references. The analog inputs are connected through two multiplexers (MUXs) to one SHA. The analog input MUXs can be switched between two sets of analog inputs between conversions. Unipolar differential conversions are possible on all channels, other than the pin used as the reference, using a reference input pin (see Figure 22-1). The Analog Input Scan mode sequentially converts user-specified channels. A control register specifies which analog input channels will be included in the scanning sequence. The 10-bit ADC is connected to a 16-word result buffer. Each 10-bit result is converted to one of eight, 32-bit output formats when it is read from the result buffer. The PIC32MX3XX/4XX 10-bit Analog-to-Digital (A/D) converter (or ADC) includes the following features: * Successive Approximation Register (SAR) conversion * Up to 1000 kilo samples per second (ksps) conversion speed * Up to 16 analog input pins * External voltage reference input pins * One unipolar, differential Sample-and-Hold Amplifier (SHA) * Automatic Channel Scan mode * Selectable conversion trigger source * 16-word conversion result buffer * Selectable Buffer Fill modes * Eight conversion result format options * Operation during CPU Sleep and Idle modes FIGURE 22-1: ADC1 MODULE BLOCK DIAGRAM VREF+(1) AVDD VREF-(1) AVSS AN0 AN15 VCFG<2:0> ADC1BUF0 ADC1BUF1 S/H + CH0SB<4:0> ADC1BUF2 VREFH SAR ADC VREFL CHANNEL SCAN CH0SA<4:0> CSCNA AN1 VREFL ADC1BUFE ADC1BUFF CH0NA CH0NB Alternate Input Selection Note 1: VREF+, VREF- inputs can be multiplexed with other analog inputs. (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 93 PIC32MX3XX/4XX FIGURE 22-2: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM ADRC ADC Internal RC Clock(1) ADCS<7:0> 8 ADC Conversion Clock Multiplier 1, 2, 3, 4, 5,..., 512 0 TAD 1 TPB X2 Note 1: See the ADC electrical characteristics for the exact RC clock value. DS61143F-page 94 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX 23.0 Note: COMPARATOR This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" Section 19. "Comparator" (DS61110) for a detailed description of this peripheral. The manual is available from the Microchip web site (www.Microchip.com/PIC32). Following are some of the key features of this module: * Selectable inputs available include: - Analog inputs multiplexed with I/O pins - On-chip internal absolute voltage reference (IVREF) - Comparator voltage reference (CVREF) * Outputs can be inverted * Selectable interrupt generation A block diagram of the comparator module is shown in Figure 23-1. The PIC32MX3XX/4XX Analog Comparator module contains one or more comparator(s) that can be configured in a variety of ways. FIGURE 23-1: COMPARATOR BLOCK DIAGRAM Comparator 1 CREF ON COUT (CM1CON) C1OUT (CMSTAT) C1IN+(2) CVREF(3) CCH<1:0> C1INC1IN+ C2IN+ IVREF(3) C1 CPOL C1OUT COE Comparator 2 CREF C2IN+ CVREF(3) CCH<1:0> C2INC2IN+ C1IN+ IVREF(3) C2 COE ON COUT (CM2CON) C2OUT (CMSTAT) CPOL C2OUT Note 1: 2: 3: IVref is the internal 1.2V reference. On USB variants, when USB is enabled, this pin is controlled by the USB module and therefore is not available as a comparator input. Internally connected. (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 95 PIC32MX3XX/4XX NOTES: DS61143F-page 96 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX 24.0 Note: COMPARATOR VOLTAGE REFERENCE (CVREF) This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" Section 20. "Comparator Voltage Reference (DS61109) for a detailed (CVREF)" description of this peripheral. The manual is available from the Microchip web site (www.Microchip.com/PIC32). A block diagram of the module is shown in Figure 24-1. The resistor ladder is segmented to provide two ranges of voltage reference values and has a power-down function to conserve power when the reference is not being used. The module's supply reference can be provided from either device VDD/VSS or an external voltage reference. The CVREF output is available for the comparators and typically available for pin output. The comparator voltage reference has the following features: * High and low range selection * Sixteen output levels available for each range * Internally connected to comparators to conserve device pins * Output can be connected to a pin The CVREF is a 16-tap, resistor ladder network that provides a selectable reference voltage. Although its primary purpose is to provide a reference for the analog comparators, it also may be used independently of them. FIGURE 24-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM VREF+ AVDD CVRSS = 1 CVRSS = 0 8R R R R CVR3:CVR0 CVREN CVREF 16 Steps 16-to-1 MUX R CVREFOUT CVRCON 8R CVRSS = 0 (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 97 PIC32MX3XX/4XX NOTES: DS61143F-page 98 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX 25.0 Note: POWER-SAVING FEATURES This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" Section 10. "Power-Saving Features" (DS61130) for a detailed description of this peripheral. The manual is available from the Microchip web site (www.Microchip.com/PIC32). * Sleep Mode: the CPU, the system clock source, and any peripherals that operate from the system clock source, are halted. Some peripherals can operate in Sleep using specific clock sources. This is the lowest power mode for the device. 25.3 Power-Saving Operation This section describes power saving for the PIC32MX3XX/4XX. The PIC32MX devices offer a total of nine methods and modes that are organized into two categories that allow the user to balance power consumption with device performance. In all of the methods and modes described in this section, power saving is controlled by software. The purpose of all power saving is to reduce power consumption by reducing the device clock frequency. To achieve this, low-frequency clock sources can be selected. In addition, the peripherals and CPU can be halted or disabled to further reduce power consumption. 25.3.1 SLEEP MODE 25.1 Power Saving with CPU Running When the CPU is running, power consumption can be controlled by reducing the CPU clock frequency, lowering the PBCLK, and by individually disabling modules. These methods are grouped into the following modes: * FRC Run mode: the CPU is clocked from the FRC clock source with or without postscalers. * LPRC Run mode: the CPU is clocked from the LPRC clock source. * SOSC Run mode: the CPU is clocked from the SOSC clock source. * Peripheral Bus Scaling mode: peripherals are clocked at programmable fraction of the CPU clock (SYSCLK). Sleep mode has the lowest power consumption of the device Power-Saving operating modes. The CPU and most peripherals are halted. Select peripherals can continue to operate in Sleep mode and can be used to wake the device from Sleep. See individual peripheral module sections for descriptions of behavior in Sleep. Sleep mode includes the following characteristics: * The CPU is halted. * The system clock source is typically shut down. See Section 25.4 "Peripheral Bus Scaling Method" for specific information. * There can be a wake-up delay based on the oscillator selection. * The Fail-Safe Clock Monitor (FSCM) does not operate during Sleep mode. * The BOR circuit, if enabled, remains operative during Sleep mode. * The WDT, if enabled, is not automatically cleared prior to entering Sleep mode. * Some peripherals can continue to operate in Sleep mode. These peripherals include I/O pins that detect a change in the input signal, WDT, ADC, UART, and peripherals that use an external clock input or the internal LPRC oscillator, e.g., RTCC and Timer 1. * I/O pins continue to sink or source current in the same manner as they do when the device is not in Sleep. * The USB module can override the disabling of the POSC or FRC. Refer to the USB section for specific details. * Some modules can be individually disabled by software prior to entering Sleep in order to further reduce consumption. 25.2 CPU Halted Methods The device supports two power-saving modes, Sleep and Idle, both of which halt the clock to the CPU. These modes operate with all clock sources, as listed below: * POSC Idle Mode: the system clock is derived from the POSC. The system clock source continues to operate. Peripherals continue to operate, but can optionally be individually disabled. * FRC Idle Mode: the system clock is derived from the FRC with or without postscalers. Peripherals continue to operate, but can optionally be individually disabled. * SOSC Idle Mode: the system clock is derived from the SOSC. Peripherals continue to operate, but can optionally be individually disabled. * LPRC Idle Mode: the system clock is derived from the LPRC. Peripherals continue to operate, but can optionally be individually disabled. This is the lowest power mode for the device with a clock running. (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 99 PIC32MX3XX/4XX The processor will exit, or `wake-up', from Sleep on one of the following events: * On any interrupt from an enabled source that is operating in Sleep. The interrupt priority must be greater than the current CPU priority. * On any form of device Reset. * On a WDT time-out. See Section 26.2 "Watchdog Timer (WDT)". If the interrupt priority is lower than or equal to current priority, the CPU will remain halted, but the PBCLK will start running and the device will enter into Idle mode. Note: 25.5 Idle Mode In the Idle mode, the CPU is halted but the System clock (SYSCLK) source is still enabled. This allows peripherals to continue operation when the CPU is halted. Peripherals can be individually configured to halt when entering Idle by setting their respective SIDL bit. Latency when exiting Idle mode is very low due to the CPU oscillator source remaining active. Notes: Changing the PBCLK divider ratio requires recalculation of peripheral timing. For example, assume the UART is configured for 9600 baud with a PB clock ratio of 1:1 and a POSC of 8 MHz. When the PB clock divisor of 1:2 is used, the input frequency to the baud clock is cut in half; therefore, the baud rate is reduced to 1/2 its former value. Due to numeric truncation in calculations (such as the baud rate divisor), the actual baud rate may be a tiny percentage different than expected. For this reason, any timing calculation required for a peripheral should be performed with the new PB clock frequency instead of scaling the previous value based on a change in PB divisor ratio. There is no FRZ mode for this module. 25.4 Peripheral Bus Scaling Method Most of the peripherals on the device are clocked using the PBCLK. The peripheral bus can be scaled relative to the SYSCLK to minimize the dynamic power consumed by the peripherals. The PBCLK divisor is controlled by PBDIV<1:0> (OSCCON<20:19>), allowing SYSCLK-to-PBCLK ratios of 1:1, 1:2, 1:4, and 1:8. All peripherals using PBCLK are affected when the divisor is changed. Peripherals such as the Interrupt Controller, DMA, Bus Matrix, and Prefetch Cache are clocked directly from SYSCLK, as a result, they are not affected by PBCLK divisor changes. Most of the peripherals on the device are clocked using the PBCLK. The peripheral bus can be scaled relative to the SYSCLK to minimize the dynamic power consumed by the peripherals. The PBCLK divisor is controlled by PBDIV<1:0> (OSCCON<20:19>), allowing SYSCLK-to-PBCLK ratios of 1:1, 1:2, 1:4, and 1:8. All peripherals using PBCLK are affected when the divisor is changed. Peripherals such as USB, Interrupt Controller, DMA, Bus Matrix, and Prefetch Cache are clocked directly from SYSCLK, as a result, they are not affected by PBCLK divisor changes Changing the PBCLK divisor affects: * The CPU to peripheral access latency. The CPU has to wait for next PBCLK edge for a read to complete. In 1:8 mode this results in a latency of one to seven SYSCLKs. * The power consumption of the peripherals. Power consumption is directly proportional to the frequency at which the peripherals are clocked. The greater the divisor, the lower the power consumed by the peripherals. To minimize dynamic power the PB divisor should be chosen to run the peripherals at the lowest frequency that provides acceptable system performance. When selecting a PBCLK divider, peripheral clock requirements such as baud rate accuracy should be taken into account. For example, the UART peripheral may not be able to achieve all baud rate values at some PBCLK divider depending on the SYSCLK value. Oscillator start-up and PLL lock delays are applied when switching to a clock source that was disabled and that uses a crystal and/or the PLL. For example, assume the clock source is switched from POSC to LPRC just prior to entering Sleep in order to save power. No oscillator start-up delay would be applied when exiting Idle. However, when switching back to POSC, the appropriate PLL and or oscillator startup/lock delays would be applied. The device enters Idle mode when the SLPEN (OSCCON<4>) bit is clear and a WAIT instruction is executed. The processor will wake or exit from Idle mode on the following events: * On any interrupt event for which the interrupt source is enabled. The priority of the interrupt event must be greater than the current priority of CPU. If the priority of the interrupt event is lower than or equal to current priority of CPU, the CPU will remain halted and the device will remain in Idle mode. * On any source of device Reset. * On a WDT time-out interrupt. See Section 26.2 "Watchdog Timer (WDT)". DS61143F-page 100 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX 26.0 Note: SPECIAL FEATURES This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. Refer to the "PIC32MX Family Reference Manual" (DS61132) for detailed descriptions of these features. The manual is available from the Microchip web site (www.Microchip.com/PIC32). 26.1 Configuration Bits The Configuration bits can be programmed to select various device configurations. PIC32MX3XX/4XX devices include several features intended to maximize application flexibility and reliability, and minimize cost through elimination of external components. These are: * * * * Flexible Device Configuration Watchdog Timer JTAG Interface In-Circuit Serial Programming (ICSP) REGISTER 26-1: r-0 -- bit 31 r-1 -- bit 23 R/P-1 bit 15 r-1 -- bit 7 Legend: DEVCFG0: DEVICE CONFIGURATION WORD 0 r-1 -- r-1 -- R/P-1 CP r-1 -- r-1 -- r-1 -- R/P-1 BWP bit 24 r-1 -- r-1 -- r-1 -- R/P-1 R/P-1 R/P-1 R/P-1 bit 16 R/P-1 R/P-1 R/P-1 r-1 -- r-1 -- r-1 -- r-1 -- bit 8 r-1 -- r-1 -- r-1 -- R/P-1 ICESEL r-1 -- R/P-1 R/P-1 bit 0 PWP<7:4> PWP<3:0> DEBUG<1:0> R = Readable bit U = Unimplemented bit bit 31 bit 30-29 bit 28 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) Reserved: Write `0' Reserved: Write `1' CP: Code-Protect bit Prevents boot and program Flash memory from being read or modified by an external programming device. 1 = Protection disabled 0 = Protection enabled Reserved: Write `1' bit 27-25 (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 101 PIC32MX3XX/4XX REGISTER 26-1: bit 24 DEVCFG0: DEVICE CONFIGURATION WORD 0 (CONTINUED) BWP: Boot Flash Write-Protect bit Prevents boot Flash memory from being modified during code execution. 1 = Boot Flash is writable 0 = Boot Flash is not writable Reserved: Write `1' PWP<7:0>: Program Flash Write-Protect bits Prevents selected program Flash memory pages from being modified during code execution. The PWP bits represent the one's compliment of the number of write protected program Flash memory pages. 11111111 = Disabled 11111110 = 0xBD00_0FFF 11111101 = 0xBD00_1FFF 11111100 = 0xBD00_2FFF 11111011 = 0xBD00_3FFF 11111010 = 0xBD00_4FFF 11111001 = 0xBD00_5FFF 11111000 = 0xBD00_6FFF 11110111 = 0xBD00_7FFF 11110110 = 0xBD00_8FFF 11110101 = 0xBD00_9FFF 11110100 = 0xBD00_AFFF 11110011 = 0xBD00_BFFF 11110010 = 0xBD00_CFFF 11110001 = 0xBD00_DFFF 11110000 = 0xBD00_EFFF 11101111 = 0xBD00_FFFF ... 01111111 = 0xBD07_FFFF Reserved: Write `1' ICESEL: In-Circuit Emulator/Debugger Communication Channel Select bit 1 = PGEC2/PGED2 pair is used 0 = PGEC1/PGED1 pair is used Reserved: Write `1' DEBUG<1:0>: Background Debugger Enable bits (forced to `11' if code-protect is enabled) 11 = Debugger disabled 10 = Debugger enabled 01 = Reserved (same as `11' setting) 00 = Reserved (same as `11' setting) bit 23-20 bit 19-12 bit 11-4 bit 3 bit 2 bit 1-0 DS61143F-page 102 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX REGISTER 26-2: r-1 -- bit 31 R/P-1 FWDTEN bit 23 R/P-1 bit 15 R/P-1 IESO bit 7 Legend: DEVCFG1: DEVICE CONFIGURATION WORD 1 r-1 -- r-1 -- r-1 -- r-1 -- r-1 -- r-1 -- r-1 -- bit 24 r-1 -- r-1 -- R/P-1 R/P-1 R/P-1 WDTPS<4:0> bit 16 R/P-1 R/P-1 R/P-1 r-1 -- R/P-1 OSCIOFNC R/P-1 R/P-1 bit 8 r-1 -- R/P-1 FSOSCEN r-1 -- r-1 -- R/P-1 R/P-1 FNOSC<2:0> bit 0 R/P-1 R/P-1 R/P-1 FCKSM<1:0> FPBDIV<1:0> POSCMD<1:0> R = Readable bit U = Unimplemented bit bit 31-24 bit 23 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) Reserved: Write `1' FWDTEN: Watchdog Timer Enable bit 1 = The WDT is enabled and cannot be disabled by software 0 = The WDT is not enabled; it can be enabled in software Reserved: Write `1' WDTPS<4:0>: Watchdog Timer Postscale Select bits 10100 = 1:1048576 10011 = 1:524288 10010 = 1:262144 10001 = 1:131072 10000 = 1:65536 01111 = 1:32768 01110 = 1:16384 01101 = 1:8192 01100 = 1:4096 01011 = 1:2048 01010 = 1:1024 01001 = 1:512 01000 = 1:256 00111 = 1:128 00110 = 1:64 00101 = 1:32 00100 = 1:16 00011 = 1:8 00010 = 1:4 00001 = 1:2 00000 = 1:1 All other combinations not shown result in operation = `10100' bit 22-21 bit 20-16 (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 103 PIC32MX3XX/4XX REGISTER 26-2: bit 15-14 DEVCFG1: DEVICE CONFIGURATION WORD 1 (CONTINUED) FCKSM<1:0>: Clock Switching and Monitor Selection Configuration bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled FPBDIV<1:0>: Peripheral Bus Clock Divisor Default Value bits 11 = PBCLK is SYSCLK divided by 8 10 = PBCLK is SYSCLK divided by 4 01 = PBCLK is SYSCLK divided by 2 00 = PBCLK is SYSCLK divided by 1 Reserved: Write `1' OSCIOFNC: CLKO Enable Configuration bit 1 = CLKO output signal active on the OSCO pin; primary oscillator must be disabled or configured for the External Clock mode (EC) for the CLKO to be active (POSCMD<1:0> = 11 OR 00) 0 = CLKO output disabled POSCMD<1:0>: Primary Oscillator Configuration bits 11 = Primary oscillator disabled 10 = HS oscillator mode selected 01 = XT oscillator mode selected 00 = External clock mode selected IESO: Internal External Switchover bit 1 = Internal External Switchover mode enabled (Two-Speed Start-up enabled) 0 = Internal External Switchover mode disabled (Two-Speed Start-up disabled) Reserved: Write `1' FSOSCEN: Secondary Oscillator Enable bit 1 = Enable Secondary Oscillator 0 = Disable Secondary Oscillator Reserved: Write `1' FNOSC<2:0>: Oscillator Selection bits 000 = Fast RC Oscillator (FRC) 001 = Fast RC Oscillator with divide-by-N with PLL module (FRCDIV+PLL) 010 = Primary Oscillator (XT, HS, EC)(1) 011 = Primary Oscillator with PLL module (XT+PLL, HS+PLL, EC+PLL) 100 = Secondary Oscillator (SOSC) 101 = Low-Power RC Oscillator (LPRC) 110 = FRCDIV16 Fast RC Oscillator with fixed divide-by-16 postscaler 111 = Fast RC Oscillator with divide-by-N (FRCDIV) Note 1: Do not disable POSC (POSCMD = 00) when using this oscillator source. bit 13-12 bit 11 bit 10 bit 9-8 bit 7 bit 6 bit 5 bit 4-3 bit 2-0 DS61143F-page 104 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX REGISTER 26-3: r-1 -- bit 31 r-1 -- bit 23 R/P-1 FUPLLEN bit 15 r-1 -- bit 7 Legend: DEVCFG2: DEVICE CONFIGURATION WORD 2 r-1 -- r-1 -- r-1 -- r-1 -- r-1 -- r-1 -- r-1 -- bit 24 r-1 -- r-1 -- r-1 -- r-1 -- R/P-1 R/P-1 FPLLODIV<2:0> bit 16 r-1 -- r-1 -- r-1 -- r-1 -- R/P-1 R/P-1 FUPLLIDIV<2:0> bit 8 R/P-1 R/P-1 FPLLMULT<2:0> R/P-1 r-1 -- R/P-1 R/P-1 FPLLIDIV<2:0> bit 0 R/P-1 R/P-1 R/P-1 R = Readable bit U = Unimplemented bit bit 31-19 bit 18-16 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) Reserved: Write `1' FPLLODIV[2:0]: Default Postscaler for PLL bits 111 = PLL output divided by 256 110 = PLL output divided by 64 101 = PLL output divided by 32 100 = PLL output divided by 16 011 = PLL output divided by 8 010 = PLL output divided by 4 001 = PLL output divided by 2 000 = PLL output divided by 1 FUPLLEN: USB PLL Enable bit 1 = Enable USB PLL 0 = Disable and bypass USB PLL Reserved: Write `1' FUPLLIDIV[2:0]: PLL Input Divider bits 111 = 12x divider 110 = 10x divider 101 = 6x divider 100 = 5x divider 011 = 4x divider 010 = 3x divider 010 = 3x divider 001 = 2x divider 000 = 1x divider Reserved: Write `1' bit 15 bit 14-11 bit 10-8 bit 7 (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 105 PIC32MX3XX/4XX REGISTER 26-3: bit 6-4 DEVCFG2: DEVICE CONFIGURATION WORD 2 (CONTINUED) FPLLMULT[2:0]: PLL Multiplier bits 111 = 24x multiplier 110 = 21x multiplier 101 = 20x multiplier 100 = 19x multiplier 011 = 18x multiplier 010 = 17x multiplier 001 = 16x multiplier 000 = 15x multiplier Reserved: Write `1' FPLLIDIV[2:0]: PLL Input Divider bits 111 = 12x divider 110 = 10x divider 101 = 6x divider 100 = 5x divider 011 = 4x divider 010 = 3x divider 001 = 2x divider 000 = 1x divider bit 3 bit 2-0 REGISTER 26-4: r-1 -- bit 31 r-1 -- bit 23 R/P-x bit 15 R/P-x bit 7 Legend: DEVCFG3: DEVICE CONFIGURATION WORD 3 r-1 -- r-1 -- r-1 -- r-1 -- r-1 -- r-1 -- r-1 -- bit 24 r-1 -- r-1 -- r-1 -- r-1 -- r-1 -- r-1 -- r-1 -- bit 16 R/P-x R/P-x R/P-x R/P-x R/P-x R/P-x R/P-x bit 8 R/P-x R/P-x R/P-x R/P-x R/P-x R/P-x R/P-x bit 0 USERID<15:8> USERID<7:0> R = Readable bit U = Unimplemented bit bit 31-16 bit 15-0 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) Reserved: Write `1' USERID<15:0>: This is a 16-bit value that is user defined and is readable via ICSPTM and JTAG DS61143F-page 106 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX REGISTER 26-5: R bit 31 R bit 23 R bit 15 R bit 7 Legend: DEVID: DEVICE AND REVISION ID REGISTER R VER<3:0> R R R R R R bit 24 R R R R R R R bit 16 R R R DEVID<15:8> bit 8 R R R DEVID<7:0> bit 0 R R R R R R R R DEVID<27:24> DEVID<23:16> R = Readable bit U = Unimplemented bit bit 31-28 bit 27-0 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) VER<3:0>: Revision Identifier bits(1) DEVID<27:0>: Device ID(1) Note: See the PIC32MX Programming Specification for a list of Revision and Device ID values. (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 107 PIC32MX3XX/4XX 26.2 Watchdog Timer (WDT) This section describes the operation of the WDT and Power-Up Timer of the PIC32MX3XX/4XX. The WDT, when enabled, operates from the internal Low-Power Oscillator (LPRC) clock source and can be used to detect system software malfunctions by resetting the device if the WDT is not cleared periodically in software. Various WDT time-out periods can be selected using the WDT postscaler. The WDT can also be used to wake the device from Sleep or Idle mode. The following are some of the key features of the WDT module: * Configuration or software controlled * User-configurable time-out period * Can wake the device from Sleep or Idle FIGURE 26-1: WATCHDOG AND POWER-UP TIMER BLOCK DIAGRAM LPRC Control PWRT Enable 1:64 Output 1 PWRT Enable WDT Enable LPRC Oscillator Clock WDTCLR = 1 WDT Enable Wake WDT Counter Reset 25-bit Counter 25 0 1 PWRT Device Reset NMI (Wake-up) Power Save Decoder FWDTPS<4:0>(DEVCFG1<20:16>) 26.3 On-Chip Voltage Regulator All PIC32MX3XX/4XX device's core and digital logic are designed to operate at a nominal 1.8V. To simplify system designs, most devices in the PIC32MX3XX/4XX incorporate an on-chip regulator providing the required core logic voltage from VDD. The internal 1.8V regulator is controlled by the ENVREG pin. Tying this pin to VDD enables the regulator, which in turn provides power to the core. A low ESR capacitor (such as tantalum) must be connected to the VDDCORE/VCAP pin (Figure 26-2). This helps to maintain the stability of the regulator. The recommended value for the filer capacitor is provided in Section 28.1 "DC Characteristics". Note: Tying the ENVREG pin to VSS disables the regulator. In this case, separate power for the core logic at a nominal 1.8V must be supplied to the device on the VDDCORE/VCAP pin. Alternately, the VDDCORE/VCAP and VDD pins can be tied together to operate at a lower nominal voltage. Refer to Figure 26-2 for possible configurations. 26.3.1 ON-CHIP REGULATOR AND POR When the voltage regulator is enabled, it takes fixed delay for it to generate output. During this time, designated as TPU, code execution is disabled. TPU is applied every time the device resumes operation after any power-down, including Sleep mode. If the regulator is disabled, a separate Power-Up Timer (PWRT) is automatically enabled. The PWRT adds a fixed delay of TPWRT at device start-up. See Section 28.0 "Electrical Characteristics" for more information on TPU AND TPWRT. It is important that the low ESR capacitor is placed as close as possible to the VDDCORE/VCAP pin. DS61143F-page 108 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX 26.3.2 ON-CHIP REGULATOR AND BOR 26.3.3 POWER-UP REQUIREMENTS When the on-chip regulator is enabled, PIC32MX3XX/4XX devices also have a simple brownout capability. If the voltage supplied to the regulator is inadequate to maintain a regulated level, the regulator Reset circuitry will generate a Brown-out Reset. This event is captured by the BOR flag bit (RCON<1>). The brown-out voltage levels are specific in Section 28.1 "DC Characteristics". The on-chip regulator is designed to meet the power-up requirements for the device. If the application does not use the regulator, then strict power-up conditions must be adhered to. While powering up, VDDCORE must never exceed VDD by 0.3 volts. FIGURE 26-2: 3.3V CONNECTIONS FOR THE ON-CHIP REGULATOR Regulator Disabled (ENVREG tied to ground): 1.8V(1) 3.3V(1) PIC32MX VDD ENVREG VDDCORE/VCAP VSS Regulator Enabled (ENVREG tied to VDD): PIC32MX VDD ENVREG VDDCORE/VCAP CEFC (10 F typ) VSS Note 1: These are typical operating voltages. Refer to Section 28.1 "DC Characteristics" for the full operating ranges of VDD and VDDCORE. (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 109 PIC32MX3XX/4XX 26.4 Programming and Diagnostics PIC32MX3XX/4XX devices provide a complete range of programming and diagnostic features that can increase the flexibility of any application using them. These features allow system designers to include: * Simplified field programmability using two-wire InCircuit Serial ProgrammingTM (ICSPTM) interfaces * Debugging using ICSP * Programming and debugging capabilities using the EJTAG extension of JTAG * JTAG boundary scan testing for device and board diagnostics PIC32MX devices incorporate two programming and diagnostic modules, and a trace controller, that provide a range of functions to the application developer. FIGURE 26-3: BLOCK DIAGRAM OF PROGRAMMING, DEBUGGING, AND TRACE PORTS PGEC1 PGED1 ICSPTM Controller PGEC2 PGED2 ICESEL TDI TDO TCK TMS JTAGEN TRCLK TRD0 TRD1 TRD2 TRD3 DEBUG<1:0> Instruction Trace Controller DEBUG<1:0> JTAG Controller Core DS61143F-page 110 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX REGISTER 26-6: r-x -- bit 31 r-x -- bit 23 r-x -- bit 15 R/W-0 DDPUSB bit 7 Legend: DDPCON: DEBUG DATA PORT CONTROL REGISTER r-x -- r-x -- r-x -- r-x -- r-x -- r-x -- r-x -- bit 24 r-x -- r-x -- r-x -- r-x -- r-x -- r-x -- r-x -- bit 16 r-x -- r-x -- r-x -- r-x -- r-x -- r-x -- r-x -- bit 8 R/W-0 DDPU1 R/W-0 DDPU2 R/W-0 DDPSPI1 R/W-1 JTAGEN R/W-0 TROEN r-x -- r-x -- bit 0 R = Readable bit U = Unimplemented bit bit 31-8 bit 7 W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown) Reserved: Write `0'; ignore read DDPUSB: Debug Data Port Enable for USB bit 1 = USB peripheral ignores USBFRZ (U1CNFG1<5>) setting 0 = USB peripheral follows USBFRZ setting. DDPU1: Debug Data Port Enable for UART1 bit 1 = UART1 peripheral ignores FRZ (U1MODE<14>) setting 0 = UART1 peripheral follows FRZ setting DDPU2: Debug Data Port Enable for UART2 bit 1 = UART2 peripheral ignores FRZ (U2MODE<14) setting 0 = UART2 peripheral follows FRZ setting DDPSPI1: Debug Data Port Enable for SPI1 bit 1 = SPI1 peripheral ignores FRZ (SPI1CON<14>) setting 0 = SPI1 peripheral follows FRZ setting JTAGEN: JTAG Port Enable bit 1 = Enable JTAG Port 0 = Disable JTAG Port TROEN: Trace Output Enable bit 1 = Enable Trace Port 0 = Disable Trace Port Reserved: Write `1'; ignore read bit 6 bit 5 bit 4 bit 3 bit 2 bit 1-0 (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 111 PIC32MX3XX/4XX NOTES: DS61143F-page 112 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX 27.0 INSTRUCTION SET Note: The PIC32MX3XX/4XX family instruction set complies with the MIPS32 Release 2 instruction set architecture. PIC32MX does not support the following features: * CoreExtend instructions * Coprocessor 1 instructions * Coprocessor 2 instructions Table 27-1 provides a summary of the instructions that are implemented by the PIC32MX3XX/4XX family core. Refer to "MIPS32(R) Architecture for Programmers Volume II: The MIPS32(R) Instruction Set" at www.mips.com for more information. TABLE 27-1: Instruction ADD ADDI ADDIU ADDU AND ANDI B BAL BEQ BEQL MIPS32(R) INSTRUCTION SET Description Function Rd = Rs + Rt Rt = Rs + Immed Rt = Rs +U Immed Rd = Rs +U Rt Rd = Rs & Rt Rt = Rs & (016 || Immed) PC += (int)offset GPR[31] = PC + 8 PC += (int)offset if Rs == Rt PC += (int)offset if Rs == Rt PC += (int)offset else Ignore Next Instruction if !Rs[31] PC += (int)offset GPR[31] = PC + 8 if !Rs[31] PC += (int)offset GPR[31] = PC + 8 if !Rs[31] PC += (int)offset else Ignore Next Instruction if !Rs[31] PC += (int)offset else Ignore Next Instruction if !Rs[31] && Rs != 0 PC += (int)offset if !Rs[31] && Rs != 0 PC += (int)offset else Ignore Next Instruction if Rs[31] || Rs == 0 PC += (int)offset Integer Add Integer Add Immediate Unsigned Integer Add Immediate Unsigned Integer Add Logical AND Logical AND Immediate Unconditional Branch (Assembler idiom for: BEQ r0, r0, offset) Branch and Link (Assembler idiom for: BGEZAL r0, offset) Branch On Equal Branch On Equal Likely(1) BGEZ BGEZAL Branch on Greater Than or Equal To Zero Branch on Greater Than or Equal To Zero And Link BGEZALL Branch on Greater Than or Equal To Zero And Link Likely(1) BGEZL Branch on Greater Than or Equal To Zero Likely(1) BGTZ BGTZL Branch on Greater Than Zero Branch on Greater Than Zero Likely(1) BLEZ Note 1: Branch on Less Than or Equal to Zero This instruction is deprecated and should not be used. (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 113 PIC32MX3XX/4XX TABLE 27-1: Instruction BLEZL MIPS32(R) INSTRUCTION SET (CONTINUED) Description Function (1) Branch on Less Than or Equal to Zero Likely if Rs[31] || Rs == 0 PC += (int)offset else Ignore Next Instruction if Rs[31] PC += (int)offset GPR[31] = PC + 8 if Rs[31] PC += (int)offset GPR[31] = PC + 8 if Rs[31] PC += (int)offset else Ignore Next Instruction if Rs[31] PC += (int)offset else Ignore Next Instruction if Rs != Rt PC += (int)offset if Rs != Rt PC += (int)offset else Ignore Next Instruction Break Exception Rd = NumLeadingOnes(Rs) Rd = NumLeadingZeroes(Rs) PC = DEPC Exit Debug Mode Rt = Status; StatusIE = 0 LO = (int)Rs / (int)Rt HI = (int)Rs % (int)Rt LO = (uns)Rs / (uns)Rt HI = (uns)Rs % (uns)Rt Stop instruction execution until execution hazards are cleared Rt = Status; StatusIE = 1 if StatusERL PC = ErrorEPC else PC = EPC StatusEXL = 0 StatusERL = 0 LL = 0 Rt = ExtractField(Rs, pos, size) Rt = InsertField(Rs, Rt, pos, size) PC = PC[31:28] || offset<<2 BLTZ BLTZAL Branch on Less Than Zero Branch on Less Than Zero And Link BLTZALL Branch on Less Than Zero And Link Likely(1) BLTZL Branch on Less Than Zero Likely(1) BNE BNEL Branch on Not Equal Branch on Not Equal Likely(1) BREAK CLO CLZ DERET DI DIV DIVU EHB Breakpoint Count Leading Ones Count Leading Zeroes Return from Debug Exception Atomically Disable Interrupts Divide Unsigned Divide Execution Hazard Barrier EI ERET Atomically Enable Interrupts Return from Exception EXT INS J Note 1: Extract Bit Field Insert Bit Field Unconditional Jump This instruction is deprecated and should not be used. DS61143F-page 114 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX TABLE 27-1: Instruction JAL JALR JALR.HB JR JR.HB LB LBU LH LHU LL MIPS32(R) INSTRUCTION SET (CONTINUED) Description Function GPR[31] = PC + 8 PC = PC[31:28] || offset<<2 Rd = PC + 8 PC = Rs Jump and Link Jump and Link Register Jump and Link Register with Hazard Barrier Jump Register Jump Register with Hazard Barrier Load Byte Unsigned Load Byte Load Halfword Unsigned Load Halfword Load Linked Word Like JALR, but also clears execution and instruction hazards PC = Rs Like JR, but also clears execution and instruction hazards Rt = (byte)Mem[Rs+offset] Rt = (ubyte))Mem[Rs+offset] Rt = (half)Mem[Rs+offset] Rt = (uhalf)Mem[Rs+offset] Rt = Mem[Rs+offset> LLbit = 1 LLAdr = Rs + offset Rt = immediate << 16 Rt = Mem[Rs+offset] Rt = Mem[PC+offset] Re = Re MERGE Mem[Rs+offset] Re = Re MERGE Mem[Rs+offset] HI | LO += (int)Rs * (int)Rt HI | LO += (uns)Rs * (uns)Rt Rt = CPR[0, Rd, sel] Rd = HI Rd = LO if Rt 1/4 0 then Rd = Rs if Rt = 0 then Rd = Rs HI | LO -= (int)Rs * (int)Rt HI | LO -= (uns)Rs * (uns)Rt CPR[0, n, Sel] = Rt HI = Rs LO = Rs HI | LO =Unpredictable Rd = ((int)Rs * (int)Rt)31..0 HI | LO = (int)Rs * (int)Rd HI | LO = (uns)Rs * (uns)Rd LUI LW LWPC LWL LWR MADD MADDU MFC0 MFHI MFLO MOVN MOVZ MSUB MSUBU MTC0 MTHI MTLO MUL MULT MULTU NOP NOR OR ORI RDHWR Note 1: Load Upper Immediate Load Word Load Word, PC relative Load Word Left Load Word Right Multiply-Add Multiply-Add Unsigned Move From Coprocessor 0 Move From HI Move From LO Move Conditional on Not Zero Move Conditional on Zero Multiply-Subtract Multiply-Subtract Unsigned Move To Coprocessor 0 Move To HI Move To LO Multiply with register write Integer Multiply Unsigned Multiply No Operation (Assembler idiom for: SLL r0, r0, r0) Logical NOR Logical OR Logical OR Immediate Read Hardware Register (if enabled by HWREna Register) This instruction is deprecated and should not be used. Rd = ~(Rs | Rt) Rd = Rs | Rt Rt = Rs | Immed Re = HWR[Rd] (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 115 PIC32MX3XX/4XX TABLE 27-1: Instruction RDPGPR ROTR ROTRV SB SC MIPS32(R) INSTRUCTION SET (CONTINUED) Description Function Rt = SGPR[SRSCtlPSS, Rd] Rd = Rtsa-1..0 || Rt31..sa Rd = RtRs-1..0 || Rt31..Rs (byte)Mem[Rs+offset] = Rt if LLbit = 1 mem[Rs+offset> = Rt Rt = LLbit Read GPR from Previous Shadow Set Rotate Word Right Rotate Word Right Variable Store Byte Store Conditional Word SDBBP SEB SEH SH SLL SLLV SLT Software Debug Break Point Sign-Extend Byte Sign-Extend Half Store Half Shift Left Logical Shift Left Logical Variable Set on Less Than Trap to SW Debug Handler Rd = SignExtend (Rs-7...0) Rd = SignExtend (Rs-15...0) (half)Mem[Rs+offset> = Rt Rd = Rt << sa Rd = Rt << Rs[4:0] if (int)Rs < (int)Rt Rd = 1 else Rd = 0 if (int)Rs < (int)Immed Rt = 1 else Rt = 0 if (uns)Rs < (uns)Immed Rt = 1 else Rt = 0 if (uns)Rs < (uns)Immed Rd = 1 else Rd = 0 Rd = (int)Rt >> sa Rd = (int)Rt >> Rs[4:0] Rd = (uns)Rt >> sa Rd = (uns)Rt >> Rs[4:0] NOP Rt = (int)Rs - (int)Rd Rt = (uns)Rs - (uns)Rd Mem[Rs+offset] = Rt Mem[Rs+offset] = Rt Mem[Rs+offset] = Rt SLTI Set on Less Than Immediate SLTIU Set on Less Than Immediate Unsigned SLTU Set on Less Than Unsigned SRA SRAV SRL SRLV SSNOP SUB SUBU SW SWL SWR SYNC Shift Right Arithmetic Shift Right Arithmetic Variable Shift Right Logical Shift Right Logical Variable Superscalar Inhibit No Operation Integer Subtract Unsigned Subtract Store Word Store Word Left Store Word Right Synchronize Orders the cached coherent and uncached loads and stores for access to the shared memory SystemCallException if Rs == Rt TrapException if Rs == (int)Immed TrapException SYSCALL TEQ TEQI Note 1: System Call Trap if Equal Trap if Equal Immediate This instruction is deprecated and should not be used. DS61143F-page 116 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX TABLE 27-1: Instruction TGE TGEI TGEIU TGEU TLT TLTI TLTIU TLTU TNE TNEI WAIT WRPGPR WSBH XOR XORI Note 1: MIPS32(R) INSTRUCTION SET (CONTINUED) Description Function if (int)Rs >= (int)Rt TrapException if (int)Rs >= (int)Immed TrapException if (uns)Rs >= (uns)Immed TrapException if (uns)Rs >= (uns)Rt TrapException if (int)Rs < (int)Rt TrapException if (int)Rs < (int)Immed TrapException if (uns)Rs < (uns)Immed TrapException if (uns)Rs < (uns)Rt TrapException if Rs != Rt TrapException if Rs != (int)Immed TrapException Trap if Greater Than or Equal Trap if Greater Than or Equal Immediate Trap if Greater Than or Equal Immediate Unsigned Trap if Greater Than or Equal Unsigned Trap if Less Than Trap if Less Than Immediate Trap if Less Than Immediate Unsigned Trap if Less Than Unsigned Trap if Not Equal Trap if Not Equal Immediate Wait for Interrupt Write to GPR in Previous Shadow Set Word Swap Bytes Within Halfwords Exclusive OR Exclusive OR Immediate This instruction is deprecated and should not be used. Go to a low power mode and stall until interrupt occurs SGPR[SRSCtlPSS, Rd> = Rt Rd = Rt23..16 || Rt31..24 || Rt7..0 || Rt15..8 Rd = Rs ^ Rt Rt = Rs ^ (uns)Immed (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 117 PIC32MX3XX/4XX NOTES: DS61143F-page 118 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX 28.0 ELECTRICAL CHARACTERISTICS This section provides an overview of PIC32MX3XX/4XX electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC32MX3XX/4XX are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these or any other conditions above the parameters indicated in the operation listings of this specification is not implied. Absolute Maximum Ratings (Note 1) Ambient temperature under bias.............................................................................................................. .-40C to +85C Storage temperature .............................................................................................................................. -65C to +150C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any combined analog and digital pin and MCLR, with respect to VSS ......................... -0.3V to (VDD + 0.3V) Voltage on any digital only pin with respect to VSS .................................................................................. -0.3V to +5.5V Voltage on VDDCORE with respect to VSS ................................................................................................... -0.3V to 2.0V Maximum current out of VSS pin(s) .......................................................................................................................300 mA Maximum current into VDD pin(s) (Note 2)............................................................................................................300 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk by all ports .......................................................................................................................200 mA Maximum current sourced by all ports (Note 2)....................................................................................................200 mA Note 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2: Maximum allowable current is a function of device maximum power dissipation (see Table 28-2). (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 119 PIC32MX3XX/4XX 28.1 DC Characteristics OPERATING MIPS VS. VOLTAGE VDD Range (in Volts) Temp. Range (in C) Max. Frequency TABLE 28-1: Characteristic PIC32MX3XX/4XX 80 MHz (Note 1) DC5 Note 1: 2.3-3.6V -40C to +85C 40 MHz maximum for PIC32MX 40MHz family variants. TABLE 28-2: THERMAL OPERATING CONDITIONS Rating Symbol Min. Typical Max. Unit PIC32MX3XX/4XX Operating Junction Temperature Range Operating Ambient Temperature Range Power Dissipation: Internal Chip Power Dissipation: PINT = VDD x (IDD - S IOH) I/O Pin Power Dissipation: I/O = S ({VDD - VOH} x IOH) + S (VOL x IOL)) Maximum Allowed Power Dissipation PDMAX (TJ - TA)/JA W TJ TA -40 -40 -- -- +125 +85 C C PD PINT + PI/O W TABLE 28-3: THERMAL PACKAGING CHARACTERISTICS Characteristics Symbol Typical Max. Unit Notes 1 1 1 Package Thermal Resistance, 100-Pin TQFP (12x12x1 mm) Package Thermal Resistance, 64-Pin TQFP (10x10x1 mm) Package Thermal Resistance, 64-Pin QFN (9x9x0,9 mm) Note 1: JA JA JA 43 47 28 -- -- -- C/W C/W C/W Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations. TABLE 28-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Characteristics Min. Typical Max. Units Conditions DC CHARACTERISTICS Param. Symbol No. Operating Voltage DC10 DC12 DC16 Supply Voltage VDD VDR VPOR RAM Data Retention Voltage (Note 1) VDD Start Voltage to Ensure Internal Power-on Reset Signal VDD Rise Rate to Ensure Internal Power-on Reset Signal 2.3 1.75 1.75 -- -- -- 3.6 -- 1.95 V V V DC17 SVDD 0.05 -- -- V/ms Note 1: This is the limit to which VDD can be lowered without losing RAM data. DS61143F-page 120 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX TABLE 28-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Max. Units Conditions DC CHARACTERISTICS Parameter No. Typical(3) Operating Current (IDD) DC20 DC20c DC21 DC21c DC22 DC22c DC23 DC23c DC24 DC24a DC24b DC25 DC25a DC25b DC25c DC26 DC26a DC26b Note 1: 8.5 4.0 23.5 16.4 48 45 55 55 -- -- -- 94 125 302 71 -- -- -- 13 -- 32 -- 61 -- 75 -- 100 130 670 -- -- -- -- 110 180 700 mA mA mA mA mA mA mA mA A A A A A A A A A A Code executing from SRAM -40C +25C +85C -40C +25C +85C Code executing from SRAM -40C +25C +85C Code executing from SRAM Code executing from SRAM Code executing from SRAM -- -- -- -- -- -- 2.3V -- 2.3V 4 MHz 20 MHz (Note 4) 60 MHz (Note 4) 80 MHz 3.3V LPRC (31 kHz) (Note 4) 3.6V 2: 3: 4: A device's IDD supply current is mainly a function of the operating voltage and frequency. Other factors, such as PBCLK (Peripheral Bus Clock) frequency, number of peripheral modules enabled, internal code execution pattern, execution from Program Flash memory vs. SRAM, I/O pin loading and switching rate, oscillator type as well as temperature can have an impact on the current consumption. The test conditions for IDD measurements are as follows: Oscillator mode = EC+PLL with OSC1 driven by external square wave from rail to rail and PBCLK divisor = 1:8. CPU, Program Flash and SRAM data memory are operational, Program Flash memory Wait states = 7, program cache and prefetch are disabled and SRAM data memory Wait states = 1. All peripheral modules are disabled (ON bit = 0). WDT and FSCM are disabled. All I/O pins are configured as inputs and pulled to VSS. MCLR = VDD. Data in "Typical" column is at 3.3V, 25C at specified operating frequency unless otherwise stated. Parameters are for design guidance only and are not tested. This parameter is characterized, but not tested in manufacturing. (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 121 PIC32MX3XX/4XX TABLE 28-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Max. Units Conditions DC CHARACTERISTICS Parameter No. Typical(2) Idle Current (IIDLE): Core OFF, Clock ON Base Current (Note 1) DC30 DC30a DC30b DC31 DC31a DC31b DC32 DC32a DC32b DC33 DC33a DC33b DC34 DC34a DC34b DC35 DC35a DC35b DC36 DC36a DC36b Note 1: -- 1.4 -- -- 13 -- -- 20 -- -- 24 -- -- -- -- 35 65 242 -- -- -- 5 -- 5 15 -- 17 22 -- 25 29 -- 32 36 62 392 -- -- -- 43 106 414 mA mA mA mA mA mA mA mA mA mA mA mA A A A A A A A A A -40C +25C +85C -40C +25C +85C -40C +25C +85C 2.3V -- 3.6V 2.3V -- 3.6V 2.3V -- 3.6V 2.3V -- 3.6V 2.3V 80 MHz 20 MHz, (Note 3) 60 MHz (Note 3) 4 MHz 3.3V LPRC (31 kHz) (Note 3) 3.6V 2: 3: The test conditions for base IDLE current measurements are as follows: System clock is enabled and PBCLK divisor = 1:8. CPU in Idle mode (CPU core halted). Only digital peripheral modules are enabled (ON bit = 1) and being clocked. WDT and FSCM are disabled. All I/O pins are configured as inputs and pulled to VSS. MCLR = VDD. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. This parameter is characterized, but not tested in manufacturing. DS61143F-page 122 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX TABLE 28-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Max. Units Conditions DC CHARACTERISTICS Parameter No. Typical(2) Power-Down Current (IPD) (Note 1) DC40 DC40a DC40b DC40c DC40d DC40e DC40g DC40f DC41 DC41a DC41b DC41c DC41d DC41e DC41f DC42 DC42a DC42b DC42c DC42e DC42f DC42g DC42 DC42a DC42b DC42c DC42e DC42f DC42g Note 1: 2: 3: 4: 5: 6: 7 24 205 25 9 25 115 200 -- -- -- 5 -- -- -- -- -- -- 23 -- -- -- -- -- -- 880 -- -- -- 30 30 300 -- 70 70 200 (Note 5) 400 10 10 10 -- 10 10 12 10 17 37 -- 10 30 44 1100 1100 1000 -- 1100 1100 1000 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A -40C +25C +85C +25C -40C +25C +70C +85C -40C +25C +85C +25C -40C +25C +85C -40C +25C +85C +25C -40C +25C +85C -40C +25C +85C ADC: IADC (Notes 3, 4) -40C +25C +85C 3.6V ADC: IADC (Notes 3, 4) 2.5V ADC: IADC (Notes 3, 4, 6) 3.6V 3.3V 2.3V RTCC + Timer1 w/32kHz Crystal: IRTCC (Notes 3, 6) RTCC + Timer1 w/32kHz Crystal: IRTCC (Note 3) RTCC + Timer1 w/32kHz Crystal: IRTCC (Note 3) 3.6V Watchdog Timer Current: IWDT (Note 3) 3.3V Watchdog Timer Current: IWDT (Note 3) 2.3V Watchdog Timer Current: IWDT (Notes 3, 6) 3.6V Base Power-Down Current 3.3V Base Power-Down Current 2.3V Base Power-Down Current (Note 6) Module Differential Current Base IPD is measured with all digital peripheral modules enabled (ON bit = 1) and being clocked, CPU clock is disabled. All I/Os are configured as outputs and pulled low. WDT and FSCM are disabled. Data in the "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled. Data is characterized at +70C and not tested. Parameter is for design guidance only. This parameter is characterized, but not tested in manufacturing. (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 123 PIC32MX3XX/4XX TABLE 28-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typical(1) Max. Units Conditions DC CHARACTERISTICS Param. Symbol No. Characteristics Input Low Voltage VIL DI10 I/O pins: with TTL Buffer with Schmitt Trigger Buffer VSS VSS VSS VSS VSS VSS VSS -- -- -- -- -- -- -- 0.15 VDD 0.2 VDD 0.2 VDD 0.2 VDD 0.2 VDD 0.3 VDD 0.8 V V V V V V V (Note 4) (Note 4) (Note 4) (Note 4) (Note 4) DI15 DI16 DI17 DI18 DI19 VIH DI20 MCLR OSC1 (XT mode) OSC1 (HS mode) SDAx, SCLx SDAx, SCLx Input High Voltage SMBus disabled (Note 4) SMBus enabled (Note 4) I/O pins: with Analog Functions Digital Only with TTL Buffer with Schmitt Trigger Buffer 0.8 VDD 0.8 VDD 0.25VDD + 0.8V 0.8 VDD 0.8 VDD 0.7 VDD 0.7 VDD 0.7 VDD 2.1 -- -- -- -- -- -- -- -- -- VDD 5.5 5.5 VDD VDD VDD 5.5 5.5 V V V V V V V V V (Note 4) (Note 4) (Note 4) (Note 4) (Note 4) (Note 4) (Note 4) DI25 DI26 DI27 DI28 DI29 MCLR OSC1 (XT mode) OSC1 (HS mode) SDAx, SCLx SDAx, SCLx SMBus disabled (Note 4) SMBus enabled, 2.3V VPIN 5.5 (Note 4) VDD = 3.3V, VPIN = VSS DI30 ICNPU IIL CNxx Pull up Current Input Leakage Current (Note 3) 50 250 400 A DI50 DI51 DI55 DI56 Note 1: 2: I/O Ports Analog Input Pins MCLR OSC1 -- -- -- -- -- -- -- -- +1 +1 +1 +1 A A A A VSS VPIN VDD, Pin at high-impedance VSS VPIN VDD, Pin at high-impedance VSS VPIN VDD VSS VPIN VDD, XT and HS modes 3: 4: Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. This parameter is characterized, but not tested in manufacturing. DS61143F-page 124 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX TABLE 28-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typical Max. Units Conditions DC CHARACTERISTICS Param. Symbol No. Characteristics Output Low Voltage VOL DO10 DO16 VOH DO20 DO26 I/O Ports OSC2/CLKO Output High Voltage -- -- -- -- -- -- -- -- -- -- -- -- 0.4 0.4 0.4 0.4 -- -- -- -- V V V V V V V V IOL = 7 mA, VDD = 3.6V IOL = 6 mA, VDD = 2.3V IOL = 3.5 mA, VDD = 3.6V IOL = 2.5 mA, VDD = 2.3V IOH = -12 mA, VDD = 3.6V IOH = -12 mA, VDD = 2.3V IOH = -12 mA, VDD = 3.6V IOH = -12 mA, VDD = 2.3V I/O Ports OSC2/CLKO 2.4 1.4 2.4 1.4 TABLE 28-10: DC CHARACTERISTICS: PROGRAM MEMORY(3) DC CHARACTERISTICS Param. Symbol No. Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Programming temperature 0C TA +70C (25C recommended) Min. Typical(1) Max. Units Conditions Characteristics Program Flash Memory D130 D131 D132 D134 D135 EP VPR VPEW TRETD IDDP TWW Cell Endurance VDD for Read VDD for Erase or Write Characteristic Retention Supply Current during Programming Word Write Cycle Time Row Write Cycle Time (Note 2) (128 words per row) Page Erase Cycle Time Chip Erase Cycle Time 1000 VMIN 3.0 20 -- 20 3 -- -- -- -- 10 -- 4.5 -- 3.6 3.6 -- -- 40 -- E/W V V -40C to +85C VMIN = Minimum operating voltage 0C to +40C Year Provided no other specifications are violated mA s 0C to +40C 0C to +40C 0C to +40C D136 TRW ms D137 Note 1: 2: TPE TCE 20 80 -- -- -- -- ms ms 0C to +40C 0C to +40C 3: Data in "Typical" column is at 3.3V, 25C unless otherwise stated. The minimum SYSCLK for row programming is 4 MHz. Care should be taken to minimize bus activities during row programming, such as suspending any memory-to-memory DMA operations. If heavy bus loads are expected, selecting Bus Matrix Arbitration mode 2 (rotating priority) may be necessary. The default Arbitration mode is mode 1 (CPU has lowest priority). Refer to PIC32MX Flash Programming Specification (DS61145) for operating conditions during programming and erase cycles. (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 125 PIC32MX3XX/4XX TABLE 28-11: PROGRAM FLASH MEMORY WAIT STATE CHARACTERISTICS DC CHARACTERISTICS Required Flash wait states Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial SYSCLK Units Comments 0 Wait State 1 Wait State 2 Wait States Note 1: 0 to 30 31 to 60 61 to 80 MHz 40 MHz maximum for PIC32MX 40MHz family variants. TABLE 28-12: COMPARATOR SPECIFICATIONS DC CHARACTERISTICS Param. Symbol No. Characteristics Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature-40C TA +85C for Industrial Min. Typical Max. Units Comments D300 D301 VIOFF VICM Input Offset Voltage Input Common Mode Voltage -- 0 7.5 -- 25 VDD mV V AVDD = VDD, AVSS = VSS AVDD = VDD, AVSS = VSS (Note 2) Max VICM = (VDD - 1)V (Note 2) AVDD = VDD, AVSS = VSS (Notes 1, 2) Comparator module is configured before setting the comparator ON bit. (Note 2) D302 D303 CMRR TRESP Common Mode Rejection Ratio Response Time 55 -- -- 150 -- 400 dB nsec D304 ON2OV Comparator Enabled to Output Valid -- -- 10 s Note 1: 2: Response time measured with one comparator input at (VDD - 1.5)/2, while the other input transitions from VSS to VDD. These parameters are characterized but not tested. TABLE 28-13: VOLTAGE REFERENCE SPECIFICATIONS DC CHARACTERISTICS Param. No. Symbol Characteristics Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature-40C TA +85C for Industrial Min. Typical Max. Units Comments D310 D311 D312 Note 1: VRES VRAA TSET Resolution Absolute Accuracy Settling Time(1) VDD/24 -- -- -- -- -- VDD/32 1/2 10 LSb LSb s Settling time measured while CVRR = 1 and CVR3:CVR0 transitions from `0000' to `1111'. This parameter is characterized, but not tested in manufacturing. DS61143F-page 126 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX TABLE 28-14: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS DC CHARACTERISTICS Param. No. Symbol Characteristics Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature-40C TA +85C for Industrial Min. Typical Max. Units Comments D320 D321 D322 VDDCORE Regulator Output Voltage CEFC TPWRT External Filter Capacitor Value 1.62 4.7 -- 1.80 10 64 1.98 -- -- V F Capacitor must be low series resistance (< 3 ohms) ENVREG = 0 ms (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 127 PIC32MX3XX/4XX 28.2 AC Characteristics and Timing Parameters The information contained in this section defines PIC32MX3XX/4XX AC characteristics and timing parameters. TABLE 28-15: AC CHARACTERISTICS AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Operating voltage VDD range. FIGURE 28-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 2 - for OSC2 Load Condition 1 - for all pins except OSC2 VDD/2 RL Pin VSS CL Pin VSS CL RL = 464 CL = 50 pF for all pins 50 pF for OSC2 pin (EC mode) TABLE 28-16: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS AC CHARACTERISTICS Param. Symbol No. Characteristics Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typical(1) Max. Units Conditions DO56 DO58 Note 1: CIO CB All I/O pins and OSC2 SCLx, SDAx -- -- -- -- 50 400 pF pF EC mode In I2CTM mode Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. FIGURE 28-2: EXTERNAL CLOCK TIMING OS20 OS30 OS31 OSC1 OS30 OS31 DS61143F-page 128 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX TABLE 28-17: EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param. Symbol No. Characteristics Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typical(1) Max. Units Conditions OS10 FOSC External CLKI Frequency (External clocks allowed only in EC and ECPLL modes) Oscillator Crystal Frequency DC 4 3 4 10 10 32 -- -- -- -- -- -- 32.768 -- 50 (Note 3) 50 (Note 5) 10 10 25 25 100 -- MHz MHz MHz MHz MHz MHz kHz -- EC (Note 5) ECPLL (Note 4) XT (Note 5) XTPLL (Notes 4, 5) HS (Note 5) HSPLL (Notes 4, 5) SOSC (Note 5) See parameter OS10 for FOSC value EC (Note 5) EC (Note 5) (Note 5) OS11 OS12 OS13 OS14 OS15 OS20 TOSC TOSC = 1/FOSC = TCY (Note 2) -- OS30 OS31 OS40 TOSL, TOSH TOSR, TOSF TOST External Clock In (OSC1) High or Low Time External Clock In (OSC1) Rise or Fall Time Oscillator Start-up Timer Period (Only applies to HS, HSPLL, XT, XTPLL and SOSC Clock Oscillator modes) Primary Clock Fail Safe Time-out Period External Oscillator Transconductance 0.45 x TOSC -- -- -- -- 1024 -- 0.05 x TOSC -- nsec nsec TOSC OS41 OS42 TFSCM GM -- -- 2 12 -- -- ms (Note 5) mA/V VDD = 3.3V TA = +25C (Note 5) Note 1: 2: 3: 4: 5: Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are characterized but are not tested. Instruction cycle period (TCY) equals the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKI pin. 40 MHz maximum for PIC32MX 40 MHz family variants. PLL input requirements: 4 MHZ FPLLIN 5 MHZ (use PLL prescaler to reduce FOSC). This parameter is characterized, but tested at 10 MHz only at manufacturing. This parameter is characterized, but not tested in manufacturing. (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 129 PIC32MX3XX/4XX TABLE 28-18: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.3V TO 3.6V) AC CHARACTERISTICS Param. Symbol No. Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Characteristics(1) Min. Typical(2) Max. Units Conditions OS50 FPLLI PLL Voltage Controlled Oscillator (VCO) Input Frequency Range On-Chip VCO System Frequency PLL Start-up Time (Lock Time) CLKO Stability (Period Jitter or Cumulative) 4 -- 5 MHz ECPLL, HSPLL, XTPLL, FRCPLL modes OS51 OS52 OS53 Note 1: 2: FSYS TLOCK DCLK 60 -- -0.25 -- -- -- 120 2 +0.25 MHz ms % Measured over 100 ms period These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. TABLE 28-19: INTERNAL FRC ACCURACY Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for industrial Min. Typical Max. Units Conditions AC CHARACTERISTICS Param. No. Characteristics Internal FRC Accuracy @ 8.00 MHz (Note 1) F20 Note 1: FRC -2 -- +2 % Frequency calibrated at 25C and 3.3V. TUN bits can be used to compensate for temperature drift. TABLE 28-20: INTERNAL RC ACCURACY AC CHARACTERISTICS Param. No. Characteristics Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typical Max. Units Conditions LPRC @ 31.25 kHz (Note 1) F21 Note 1: -15 -- +15 % Change of LPRC frequency as VDD changes. DS61143F-page 130 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX FIGURE 28-3: I/O Pin (Input) DI35 DI40 I/O Pin (Output) Note: Refer to Figure 28-1 for load conditions. I/O TIMING CHARACTERISTICS DO31 DO32 TABLE 28-21: I/O TIMING REQUIREMENTS AC CHARACTERISTICS Param. No. Symbol Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Characteristics(2) Min. Typical(1) Max. Units Conditions DO31 DO32 DI35 DI40 Note 1: 2: TIOR TIOF TINP TRBP Port Output Rise Time Port Output Fall Time INTx Pin High or Low Time CNx High or Low Time (input) -- -- 10 2 5 5 -- -- 10 10 -- -- nsec nsec nsec TSYSCLK Data in "Typical" column is at 3.3V, 25C unless otherwise stated. This parameter is characterized, but not tested in manufacturing. (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 131 PIC32MX3XX/4XX FIGURE 28-4: POWER-ON RESET TIMING CHARACTERISTICS Internal Voltage Regulator Enabled Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC) VDD VPOR (TSYSDLY) SY02 Power Up Sequence (Note 2) SY00 (TPU) (Note 1) CPU starts fetching code Internal Voltage Regulator Enabled Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC) VDD VPOR (TSYSDLY) SY02 Power Up Sequence (Note 2) SY00 (TPU) (Note 1) SY10 (TOST) CPU starts fetching code External VDDCORE Provided Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC) VDD VPOR VDDCORE (TSYSDLY) SY02 Power Up Sequence (Note 3) SY01 (TPWRT) (Note 1) CPU starts fetching code Note 1: The Power-up period will be extended if the Power-up sequence completes before the device exits from BOR (VDD < VDDMIN). 2: Includes interval voltage regulator stabilization delay. 3: Power-Up Timer (PWRT); only active when the internal voltage regulator is disabled DS61143F-page 132 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX FIGURE 28-5: EXTERNAL RESET TIMING CHARACTERISTICS Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC) MCLR TMCLR (SY20) BOR TBOR (SY30) Reset Sequence (TSYSDLY) SY02 CPU starts fetching code Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC) Reset Sequence (TSYSDLY) SY02 TOST (SY10) CPU starts fetching code TABLE 28-22: RESETS TIMING AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typical(2) Max. Units s Conditions SY00 SY01 TPU TPWRT Power-up Period Internal Voltage Regulator Enabled Power-up Period External VDDCORE Applied (Power-Up-Timer Active) -- 48 400 64 600 80 -40C to +85C -40C to +85C ms SY02 TSYSDLY System Delay Period: Time required to reload Device Configuration Fuses plus SYSCLK delay before first instruction is fetched. TMCLR TBOR MCLR Pulse Width (low) BOR Pulse Width (low) -- 1 s + -- -- -40C to +85C 8 SYSCLK cycles -- -- 2 1 -- -- s s SY20 SY30 Note 1: 2: -40C to +85C -40C to +85C These parameters are characterized, but not tested in manufacturing. Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Characterized by design but not tested. (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 133 PIC32MX3XX/4XX FIGURE 28-6: TxCK Tx10 Tx15 OS60 TMRx Note: Refer to Figure 28-1 for load conditions. TIMER1, 2, 3, 4, 5 EXTERNAL CLOCK TIMING CHARACTERISTICS Tx11 Tx20 TABLE 28-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1) AC CHARACTERISTICS Param. Symbol No. Characteristics(2) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typical Max. Units Conditions TA10 TTXH TxCK High Time Synchronous, with prescaler Asynchronous, with prescaler [(12.5nsec or 1TPB) / N] + 25nsec 10 [(12.5nsec or 1TPB) / N] + 25nsec 10 [(25nsec or 2TPB) / N] + 50nsec 20 -- -- -- -- -- -- -- -- -- -- -- -- nsec Must also meet parameter TA15. nsec nsec Must also meet parameter TA15. nsec nsec nsec N = prescale value (1, 8, 64, 256) kHz TA11 TTXL TxCK Low Time Synchronous, with prescaler Asynchronous, with prescaler TA15 TTXP TxCK Synchronous, Input Period with prescaler Asynchronous, with prescaler OS60 FT1 SOSC1/T1CK Oscillator Input Frequency Range (oscillator enabled by setting TCS bit (T1CON<1>)) Delay from External TxCK Clock Edge to Timer Increment 32 -- 100 TA20 TCKEXTMRL -- 1 TPB Note 1: 2: Timer1 is a Type A. This parameter is characterized, but not tested in manufacturing. DS61143F-page 134 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX TABLE 28-24: TIMER2, 3, 4, 5 EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param. Symbol No. Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Max. Units Conditions Characteristics(1) TB10 TTXH TxCK High Time TxCK Low Time Synchronous, with prescaler Synchronous, with prescaler [(12.5nsec or 1TPB) / N] + 25nsec [(12.5nsec or 1TPB) / N] + 25nsec [(25nsec or 2TPB) / N] + 50nsec -- -- nsec TB11 TTXL -- nsec Must also meet N = prescale value parameter (1, 2, 4, 8, 16, TB15. Must also meet 32, 64, 256) parameter TB15. TB15 TB20 TTXP TxCK Synchronous, Input Period with prescaler -- 1 nsec TPB TCKEXT- Delay from External TxCK Clock Edge to Timer IncreMRL ment Note 1: These parameters are characterized, but not tested in manufacturing. FIGURE 28-7: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS ICx IC10 IC15 Note: Refer to Figure 28-1 for load conditions. IC11 TABLE 28-25: INPUT CAPTURE MODULE TIMING REQUIREMENTS AC CHARACTERISTICS Param. Symbol No. Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Max. Units Conditions Characteristics(1) IC10 TCCL ICx Input Low Time [(12.5nsec or 1TPB) / N] + 25nsec -- nsec Must also meet parameter IC15. Must also meet parameter IC15. N = prescale value (1, 4, 16) IC11 TCCH ICx Input High Time [(12.5nsec or 1TPB) / N] + 25nsec -- nsec IC15 Note 1: TCCP ICx Input Period [(25nsec or 2TPB) / N] + 50nsec -- nsec These parameters are characterized, but not tested in manufacturing. (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 135 PIC32MX3XX/4XX FIGURE 28-8: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS OCx (Output Compare or PWM Mode) OC11 OC10 Note: Refer to Figure 28-1 for load conditions. TABLE 28-26: OUTPUT COMPARE MODULE TIMING REQUIREMENTS AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typical(2) Max. Units Conditions OC10 OC11 Note 1: 2: TCCF TCCR OCx Output Fall Time OCx Output Rise Time -- -- -- -- -- -- nsec nsec See parameter DO32. See parameter DO31. These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. FIGURE 28-9: OC/PWM MODULE TIMING CHARACTERISTICS OC20 OCFA/OCFB OC15 OCx Note: Refer to Figure 28-1 for load conditions. TABLE 28-27: SIMPLE OC/PWM MODE TIMING REQUIREMENTS AC CHARACTERISTICS Param No. Symbol Characteristics(1) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min Typical(2) Max Units Conditions OC15 OC20 Note 1: 2: TFD TFLT Fault Input to PWM I/O Change Fault Input Pulse Width -- 50 -- -- 25 -- nsec nsec These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. DS61143F-page 136 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX FIGURE 28-10: SCKx (CKP = 0) SP11 SCKx (CKP = 1) SP35 SP20 MSb SP31 SDIx MSb In SP40 SP41 Bit 14 - - - -1 Bit 14 - - - - - -1 SP30 LSb In SP21 LSb SP10 SP21 SP20 SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS SDOx Note: Refer to Figure 28-1 for load conditions. TABLE 28-28: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typical(2) Max. Units Conditions SP10 SP11 SP20 SP21 SP30 SP31 SP35 SP40 SP41 Note 1: 2: 3: 4: TSCL TSCH TSCF TSCR TDOF TDOR SCKx Output Low Time (Note 3) SCKx Output High Time (Note 3) SCKx Output Fall Time (Note 4) SCKx Output Rise Time (Note 4) SDOx Data Output Fall Time (Note 4) SDOx Data Output Rise Time (Note 4) TSCK/2 TSCK/2 -- -- -- -- -- 10 10 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15 -- -- nsec nsec nsec nsec nsec nsec nsec nsec nsec See parameter DO32. See parameter DO31. See parameter DO32. See parameter DO31. TSCH2DOV, SDOx Data Output Valid after TSCL2DOV SCKx Edge TDIV2SCH, TDIV2SCL TSCH2DIL, TSCL2DIL Setup Time of SDIx Data Input to SCKx Edge Hold Time of SDIx Data Input to SCKx Edge These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 40 nsec. Therefore, the clock generated in Master mode must not violate this specification. Assumes 50 pF load on all SPIx pins. (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 137 PIC32MX3XX/4XX FIGURE 28-11: SCKX (CKP = 0) SP11 SCKX (CKP = 1) SP10 SP21 SP20 SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS SP36 SP35 SP20 MSb Bit 14 - - - - - -1 SP30,SP31 LSb SP21 SDOX SDIX SP40 MSb In SP41 Bit 14 - - - -1 LSb In Note: Refer to Figure 28-1 for load conditions. TABLE 28-29: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85Cfor Industrial Min. Typical(2) Max. Units Conditions SP10 SP11 SP20 SP21 SP30 SP31 SP35 SP36 SP40 Note 1: 2: 3: 4: TSCL TSCH TSCF TSCR TDOF TDOR SCKx Output Low Time (Note 3) SCKx Output High Time (Note 3) SCKx Output Fall Time (Note 4) SCKx Output Rise Time (Note 4) SDOx Data Output Fall Time (Note 4) SDOx Data Output Rise Time (Note 4) TSCK/2 TSCK/2 -- -- -- -- -- 15 10 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15 -- -- nsec nsec nsec nsec nsec nsec nsec nsec nsec See parameter DO32. See parameter DO31. See parameter DO32. See parameter DO31. TSCH2DOV, SDOx Data Output Valid after TSCL2DOV SCKx Edge TDOV2SC, SDOx Data Output Setup to TDOV2SCL First SCKx Edge TDIV2SCH, Setup Time of SDIx Data Input TDIV2SCL to SCKx Edge These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 40 nsec. Therefore, the clock generated in Master mode must not violate this specification. Assumes 50 pF load on all SPIx pins. DS61143F-page 138 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX TABLE 28-29: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS (CONTINUED) AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85Cfor Industrial Min. Typical(2) Max. Units Conditions SP41 Note 1: 2: 3: 4: TSCH2DIL, TSCL2DIL Hold Time of SDIx Data Input to SCKx Edge 10 -- -- nsec These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 40 nsec. Therefore, the clock generated in Master mode must not violate this specification. Assumes 50 pF load on all SPIx pins. FIGURE 28-12: SSX SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS SP50 SCKX (CKP = 0) SP71 SCKX (CKP = 1) SP35 SDOX MSb SP72 SP73 SP70 SP73 SP72 SP52 Bit 14 - - - - - -1 SP30,SP31 LSb SP51 LSb In SDIX SP40 MSb In SP41 Bit 14 - - - -1 Note: Refer to Figure 28-1 for load conditions. (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 139 PIC32MX3XX/4XX TABLE 28-30: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typical(2) Max. Units Conditions SP70 SP71 SP72 SP73 SP30 SP31 SP35 SP40 SP41 SP50 SP51 TSCL TSCH TSCF TSCR TDOF TDOR SCKx Input Low Time (Note 3) SCKx Input High Time (Note 3) SCKx Input Fall Time SCKx Input Rise Time SDOx Data Output Fall Time (Note 4) SDOx Data Output Rise Time (Note 4) TSCK/2 TSCK/2 -- -- -- -- -- 10 10 60 5 -- -- 5 5 -- -- -- -- -- -- -- -- -- 10 10 -- -- 15 -- -- -- 25 nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec See parameter DO32. See parameter DO31. TSCH2DOV, SDOx Data Output Valid after TSCL2DOV SCKx Edge TDIV2SCH, Setup Time of SDIx Data Input TDIV2SCL to SCKx Edge TSCH2DIL, TSCL2DIL Hold Time of SDIx Data Input to SCKx Edge TSSL2SCH, SSx to SCKx or SCKx Input TSSL2SCL TSSH2DOZ SSx to SDOx Output High-Impedance (Note 3) TSCH2SSH SSx after SCKx Edge TSCL2SSH SP52 Note 1: 2: 3: 4: TSCK + 20 -- -- nsec -- These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 40 nsec. Assumes 50 pF load on all SPIx pins. DS61143F-page 140 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX FIGURE 28-13: SSx SP50 SCKx (CKP = 0) SP71 SCKx (CKP = 1) SP35 SP52 SDOx MSb Bit 14 - - - - - -1 SP30,SP31 SDIx SDI SP40 MSb In SP41 Bit 14 - - - -1 LSb In SP72 LSb SP51 SP73 SP70 SP73 SP72 SP52 SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS SP60 Note: Refer to Figure 28-1 for load conditions. TABLE 28-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typical(2) Max. Units Conditions SP70 SP71 SP72 SP73 SP30 SP31 SP35 SP40 SP41 Note 1: 2: 3: 4: TSCL TSCH TSCF TSCR TDOF TDOR SCKx Input Low Time (Note 3) SCKx Input High Time (Note 3) SCKx Input Fall Time SCKx Input Rise Time SDOx Data Output Fall Time (Note 4) SDOx Data Output Rise Time (Note 4) TSCK/2 TSCK/2 -- -- -- -- -- 10 10 -- -- 5 5 -- -- -- -- -- -- -- 10 10 -- -- 15 -- -- nsec nsec nsec nsec nsec nsec nsec nsec nsec See parameter DO32. See parameter DO31. TSCH2DOV, SDOx Data Output Valid after TSCL2DOV SCKx Edge TDIV2SCH, Setup Time of SDIx Data Input TDIV2SCL to SCKx Edge TSCH2DIL, TSCL2DIL Hold Time of SDIx Data Input to SCKx Edge These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 40 nsec. Assumes 50 pF load on all SPIx pins. (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 141 PIC32MX3XX/4XX TABLE 28-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS (CONTINUED) AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typical(2) Max. Units Conditions SP50 SP51 TSSL2SCH, SSx to SCKx or SCKx TSSL2SCL Input TSSH2DOZ SSx to SDOX Output High-Impedance (Note 4) TSCH2SSH SSx after SCKx Edge TSCL2SSH TSSL2DOV SDOx Data Output Valid after SSx Edge 60 5 -- -- -- 25 nsec nsec SP52 SP60 Note 1: 2: 3: 4: TSCK + 20 -- -- -- -- 25 nsec nsec These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 40 nsec. Assumes 50 pF load on all SPIx pins. FIGURE 28-14: SCLx I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) IM31 IM30 IM33 IM34 SDAx Start Condition Note: Refer to Figure 28-1 for load conditions. Stop Condition FIGURE 28-15: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM11 IM10 IM11 IM26 IM21 SCLx IM10 IM25 IM33 SDAx In IM40 IM40 IM45 SDAx Out Note: Refer to Figure 28-1 for load conditions. DS61143F-page 142 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX TABLE 28-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) AC CHARACTERISTICS Param. Symbol No. Characteristics Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min.(1) Max. Units s s s s s s Conditions IM10 TLO:SCL Clock Low Time 100 kHz mode 400 kHz mode 1 MHz mode (Note 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) -- 20 + 0.1 CB -- -- 20 + 0.1 CB -- 250 100 100 0 0 0 TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) -- -- -- -- -- -- 300 300 100 1000 300 300 -- -- -- -- 0.9 0.3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CB is specified to be from 10 to 400 pF. IM11 THI:SCL Clock High Time 100 kHz mode 400 kHz mode 1 MHz mode (Note 2) IM20 TF:SCL SDAx and SCLx 100 kHz mode Fall Time 400 kHz mode 1 MHz mode (Note 2) nsec nsec nsec nsec nsec nsec nsec nsec nsec s s s s s s s s s s s s IM21 TR:SCL SDAx and SCLx 100 kHz mode Rise Time 400 kHz mode 1 MHz mode (Note 2) CB is specified to be from 10 to 400 pF. IM25 TSU:DAT Data Input Setup Time 100 kHz mode 400 kHz mode 1 MHz mode (Note 2) -- IM26 THD:DAT Data Input Hold Time 100 kHz mode 400 kHz mode 1 MHz mode (Note 2) -- IM30 TSU:STA Start Condition Setup Time 100 kHz mode 400 kHz mode 1 MHz mode (Note 2) Only relevant for Repeated Start condition. IM31 THD:STA Start Condition Hold Time 100 kHz mode 400 kHz mode 1 MHz mode (Note 2) After this period, the first clock pulse is generated. IM33 TSU:STO Stop Condition Setup Time 100 kHz mode 400 kHz mode 1 MHz mode (Note 2) -- IM34 THD:STO Stop Condition Hold Time 100 kHz mode 400 kHz mode 1 MHz mode (Note 2) nsec nsec nsec -- Note 1: 2: BRG is the value of the I2CTM Baud Rate Generator. Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 143 PIC32MX3XX/4XX TABLE 28-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) (CONTINUED) AC CHARACTERISTICS Param. Symbol No. Characteristics Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min.(1) Max. Units Conditions IM40 TAA:SCL Output Valid From Clock 100 kHz mode 400 kHz mode 1 MHz mode (Note 2) -- -- -- 4.7 1.3 0.5 -- 3500 1000 350 -- -- -- 400 nsec nsec nsec s s s -- -- -- The amount of time the bus must be free before a new transmission can start. IM45 TBF:SDA Bus Free Time 100 kHz mode 400 kHz mode 1 MHz mode (Note 2) IM50 Note 1: 2: CB Bus Capacitive Loading I2CTM pF BRG is the value of the Baud Rate Generator. Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). FIGURE 28-16: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCLx IS31 IS30 IS33 IS34 SDAx Start Condition Note: Refer to Figure 28-1 for load conditions. Stop Condition FIGURE 28-17: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS11 IS10 IS30 IS26 IS21 SCLx IS31 IS25 IS33 SDAx In IS40 IS40 IS45 SDAx Out Note: Refer to Figure 28-1 for load conditions. DS61143F-page 144 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX TABLE 28-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) AC CHARACTERISTICS Param. No. Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Characteristics Min. Max. Units s s s s s s Conditions Symbol IS10 TLO:SCL Clock Low Time 100 kHz mode 400 kHz mode 1 MHz mode (Note 1) 4.7 1.3 0.5 4.0 0.6 0.5 -- 20 + 0.1 CB -- -- 20 + 0.1 CB -- 250 100 100 0 0 0 4700 600 250 4000 600 250 4000 600 600 -- -- -- -- -- -- 300 300 100 1000 300 300 -- -- -- -- 0.9 0.3 -- -- -- -- -- -- -- -- -- PBCLK must operate at a minimum of 800 KHz. PBCLK must operate at a minimum of 3.2 MHz. IS11 THI:SCL Clock High Time 100 kHz mode 400 kHz mode 1 MHz mode (Note 1) PBCLK must operate at a minimum of 800 KHz. PBCLK must operate at a minimum of 3.2 MHz. IS20 TF:SCL SDAx and SCLx Fall Time 100 kHz mode 400 kHz mode 1 MHz mode (Note 1) nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec s s s s s s s s s s s CB is specified to be from 10 to 400 pF. IS21 TR:SCL SDAx and SCLx Rise Time 100 kHz mode 400 kHz mode 1 MHz mode (Note 1) CB is specified to be from 10 to 400 pF. IS25 TSU:DAT Data Input Setup Time 100 kHz mode 400 kHz mode 1 MHz mode (Note 1) IS26 THD:DAT Data Input Hold Time 100 kHz mode 400 kHz mode 1 MHz mode (Note 1) IS30 TSU:STA Start Condition Setup Time 100 kHz mode 400 kHz mode 1 MHz mode (Note 1) Only relevant for Repeated Start condition. IS31 THD:STA Start Condition Hold Time 100 kHz mode 400 kHz mode 1 MHz mode (Note 1) After this period, the first clock pulse is generated. IS33 TSU:STO Stop Condition Setup Time 100 kHz mode 400 kHz mode 1 MHz mode (Note 1) Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 145 PIC32MX3XX/4XX TABLE 28-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) (CONTINUED) AC CHARACTERISTICS Param. No. Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Characteristics Min. Max. Units Conditions Symbol IS34 THD:STO Stop Condition Hold Time 100 kHz mode 400 kHz mode 1 MHz mode (Note 1) 4000 600 250 0 0 0 4.7 1.3 0.5 -- -- -- nsec nsec nsec IS40 TAA:SCL Output Valid From 100 kHz mode Clock 400 kHz mode 1 MHz mode (Note 1) 3500 1000 350 -- -- -- 400 nsec nsec nsec s s s IS45 TBF:SDA Bus Free Time 100 kHz mode 400 kHz mode 1 MHz mode (Note 1) The amount of time the bus must be free before a new transmission can start. IS50 Note 1: CB Bus Capacitive Loading pF Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). TABLE 28-34: ADC MODULE SPECIFICATIONS AC CHARACTERISTICS Param. No. Symbol Characteristics Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typical Max. Units Conditions Device Supply AD01 AVDD Module VDD Supply Greater of VDD - 0.3 or 2.5 VSS AVSS + 2.0 2.5 AVSS 2.0 -- Lesser of VDD + 0.3 or 3.6 VSS + 0.3 AVDD 3.6 VREFH - 2.0 AVDD V AD02 AD05 AD05a AD06 AD07 AVSS VREFH VREFL VREF Module VSS Supply Reference Voltage High Reference Voltage Low Absolute Reference Voltage (VREFH - VREFL) Current Drain -- -- -- -- -- V V V V V (Note 1) Reference Inputs VREFH = AVDD (Note 3) (Note 1) (Note 3) AD08 IREF -- 250 -- -- 400 3 VREFH AVDD/2 A A ADC operating ADC off Analog Input AD12 VINH-VINL Full-Scale Input Span VINL Absolute VINL Input Voltage VREFL AVSS - 0.3 V V Note 1: 2: 3: These parameters are not characterized or tested in manufacturing. With no missing codes. These parameters are characterized, but not tested in manufacturing. DS61143F-page 146 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX TABLE 28-34: ADC MODULE SPECIFICATIONS (CONTINUED) AC CHARACTERISTICS Param. No. Symbol Characteristics Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typical Max. Units Conditions VIN Absolute Input Voltage Leakage Current AVSS - 0.3 -- +/- 0.001 AVDD + 0.3 +/-0.610 V A VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V Source Impedance = 10K (Note 1) AD17 RIN Recommended Impedance of Analog Voltage Source Resolution Integral Nonlinearity Differential Nonlinearity -- -- 5K ADC Accuracy - Measurements with External VREF+/VREF- AD20c Nr AD21c INL AD22c DNL 10 data bits -- -- -- -- <+/-1 <+/-1 bits LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V (Note 2) LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V LSb VINL = AVSS = 0V, AVDD = 3.3V -- bits <+/-1 Guaranteed (Note 3) AD23c GERR AD24n EOFF AD25c -- AD20d Nr AD21d INL Gain Error Offset Error Monotonicity Resolution Integral Nonlinearity -- -- -- -- -- -- 10 data bits <+/-1 <+/-1 -- ADC Accuracy - Measurements with Internal VREF+/VREF- -- -- LSb VINL = AVSS = 0V, AVDD = 2.5V to 3.6V (Note 3) LSb VINL = AVSS = 0V, AVDD = 2.5V to 3.6V (Notes 2, 3) LSb VINL = AVSS = 0V, AVDD = 2.5V to 3.6V (Note 3) LSb VINL = AVSS = 0V, AVDD = 2.5V to 3.6V (Note 3) -- Guaranteed AD22d DNL Differential Nonlinearity -- -- <+/-1 AD23d GERR Gain Error -- -- <+/-4 AD24d EOFF Offset Error -- -- <+/-2 AD25d Note 1: 2: 3: -- Monotonicity -- -- -- These parameters are not characterized or tested in manufacturing. With no missing codes. These parameters are characterized, but not tested in manufacturing. (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 147 PIC32MX3XX/4XX TABLE 28-35: 10-BIT CONVERSION RATE PARAMETERS PIC32MX 10-bit A/D Converter Conversion Rates (Note 2) ADC Speed TAD Sampling RS Max Minimum Time Min VDD Temperature ADC Channels Configuration 1 MIPS to 400 ksps (Note 1) 65 ns 132 ns 500 3.0V to 3.6V -40C to +85C VREF- VREF+ ANx CHX SHA ADC Up to 400 ksps 200 ns 200 ns 5.0 k 2.5V to 3.6V -40C to +85C VREF- VREF+ or or AVSS AVDD CHX SHA ANx or VREFADC ANx Up to 300 ksps 200 ns 200 ns 5.0 k 2.5V to 3.6V -40C to +85C VREF- VREF+ or or AVSS AVDD CHX SHA ANx or VREFADC ANx Note 1: 2: External VREF- and VREF+ pins must be used for correct operation. These parameters are characterized, but not tested in manufacturing. DS61143F-page 148 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX TABLE 28-36: A/D CONVERSION TIMING REQUIREMENTS AC CHARACTERISTICS Param. Symbol No. Clock Parameters Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Characteristics Min. Typical(1) Max. Units Conditions AD50 AD51 AD55 AD56 AD57 TAD TRC A/D Clock Period (Note 2) A/D Internal RC Oscillator Period Conversion Time Throughput Rate (Sampling Speed) Sample Time 65 -- -- -- -- 1 -- 250 12 TAD -- -- -- -- -- -- 1000 400 31 nsec nsec -- KSPS KSPS TAD See Table 28-35. (Note 3) Conversion Rate TCONV -- AVDD = 3.0V to 3.6V AVDD = 2.5V to 3.6V TSAMP must be 132 nsec. Auto-Convert Trigger (SSRC<2:0> = 111) not selected. -- -- FCNV TSAMP Timing Parameters AD60 TPCS Conversion Start from Sample Trigger(3) Sample Start from Setting Sample (SAMP) bit Conversion Completion to Sample Start (ASAM = 1) (Note 3) Time to Stabilize Analog Stage from A/D OFF to A/D ON (Note 3) -- 1.0 TAD -- -- AD61 AD62 TPSS TCSS 0.5 TAD -- -- 0.5 TAD 1.5 TAD -- -- -- AD63 TDPU -- -- 2 s -- Note 1: 2: 3: These parameters are characterized, but not tested in manufacturing. Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. Characterized by design but not tested. (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 149 PIC32MX3XX/4XX FIGURE 28-18: A/D CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000) AD50 ADCLK Instruction Execution Set SAMP SAMP ch0_dischrg ch0_samp ch1_dischrg ch1_samp eoc AD61 AD60 TSAMP CONV ADxIF Buffer(0) Buffer(1) AD55 AD55 Clear SAMP 1 2 3 4 5 6 7 8 5 6 7 8 1 - Software sets ADxCON. SAMP to start sampling. 2 - Sampling starts after discharge period. TSAMP is described in the "PIC32MX Family Reference Manual" (DS61132). 3 - Software clears ADxCON. SAMP to start conversion. 4 - Sampling ends, conversion sequence starts. 5 - Convert bit 9. 6 - Convert bit 8. 7 - Convert bit 0. 8 - One TAD for end of conversion. DS61143F-page 150 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX FIGURE 28-19: A/D CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001 AD50 ADCLK Instruction Execution SAMP ch0_dischrg ch0_samp ch1_dischrg ch1_samp eoc Set ADON TSAMP CONV ADxIF Buffer(0) Buffer(1) AD55 AD55 TSAMP TCONV 1 2 3 4 5 6 7 3 4 5 6 8 3 4 1 - Software sets ADxCON. ADON to start AD operation. 2 - Sampling starts after discharge period. TSAMP is described in the "PIC32MX Family Reference Manual" (DS61132). 3 - Convert bit 9. 4 - Convert bit 8. 5 - Convert bit 0. 6 - One TAD for end of conversion. 7 - Begin conversion of next channel. 8 - Sample for time specified by SAMC<4:0>. (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 151 PIC32MX3XX/4XX FIGURE 28-20: CS PARALLEL SLAVE PORT TIMING PS5 RD PS6 WR PS4 PMD<7:0> PS7 PS3 PS1 PS2 TABLE 28-37: PARALLEL SLAVE PORT REQUIREMENTS AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typical Max. Units Conditions PS1 PS2 PS3 PS4 PS5 PS6 PS7 Note 1: TdtV2wrH Data In Valid before WR or CS Inactive (setup time) TwrH2dtI TrdL2dtV TrdH2dtI Tcs TWR TRD WR or CS Inactive to Data- In Invalid (hold time) RD and CS Active to Data- Out Valid RD Active or CS Inactive to Data- Out Invalid CS Active Time WR Active Time RD Active Time 20 20 -- 0 25 25 25 -- -- -- -- -- -- -- -- -- 60 10 -- -- -- nsec nsec nsec nsec nsec nsec nsec These parameters are characterized, but not tested in manufacturing. DS61143F-page 152 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX FIGURE 28-21: PARALLEL MASTER PORT READ TIMING DIAGRAM TPB TPB TPB TPB TPB TPB TPB TPB PB Clock PM4 PMA<13:18> Address PM6 PMD<7:0> Address<7:0> Address<7:0> PM2 PM3 PMRD PM5 PMWR PM1 PMALL/PMALH PM7 Data Data PMCS<2:1> TABLE 28-38: PARALLEL MASTER PORT READ TIMING REQUIREMENTS AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typical Max. Units Conditions PM1 PM2 PM3 PM4 PM5 PM6 PM7 Note 1: TLAT TADSU PMALL/PMALH Pulse Width Address Out Valid to PMALL/PMALH Invalid (address setup time) -- -- -- 1 -- 5 -- 1 TPB 2 TPB 1 TPB -- 1 TPB -- 0 -- -- -- -- -- -- -- -- -- -- nsec -- nsec nsec TADHOLD PMALL/PMALH Invalid to Address Out Invalid (address hold time) TAHOLD TRD TDSU TDHOLD PMRD Inactive to Address Out Invalid (address hold time) PMRD Pulse Width PMRD or PMENB Active to Data In Valid (data setup time) PMRD or PMENB Inactive to Data In Invalid (data hold time) These parameters are characterized, but not tested in manufacturing. (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 153 PIC32MX3XX/4XX FIGURE 28-22: PARALLEL MASTER PORT WRITE TIMING DIAGRAM TPB TPB TPB TPB TPB TPB TPB TPB PB Clock Address PM2 + PM3 PMD<7:0> Address<7:0> PM12 PMRD PM11 PMWR PM1 PMALL/PMALH Data PM13 PMA<13:18> PMCS<2:1> TABLE 28-39: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typical Max. Units Conditions PM11 PM12 PM13 Note 1: TWR TDVSU PMWR Pulse Width Data Out Valid before PMWR or PMENB goes Inactive (data setup time) -- -- -- 1 TPB 2 TPB 1 TPB -- -- -- -- -- -- TDVHOLD PMWR or PMEMB Invalid to Data Out Invalid (data hold time) These parameters are characterized, but not tested in manufacturing. DS61143F-page 154 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX TABLE 28-40: OTG ELECTRICAL SPECIFICATIONS AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typ Max. Units Conditions USB313 VUSB USB Voltage 3.0 -- 3.6 V Voltage on bus must be in this range for proper USB operation. USB315 VILUSB USB316 VIHUSB USB318 VDIFS USB319 VCM Input Low Voltage for USB Buffer Input High Voltage for USB Buffer Differential Input Sensitivity Differential Common Mode Range -- 2.0 -- 0.8 -- -- -- -- 0.8 -- 0.2 2.5 V V V V The difference between D+ and Dmust exceed this value while VCM is met. 1.5 k load connected to 3.6V 1.5 k load connected to ground USB320 ZOUT USB321 VOL USB322 VOH Note 1: Driver Output Impedance Voltage Output Low Voltage Output High 28.0 0.0 2.8 -- -- -- 44.0 0.3 3.6 V V These parameters are characterized, but not tested in manufacturing. FIGURE 28-23: EJTAG TIMING CHARACTERISTICS TTCKeye TTCKhigh TTCKlow Trf TCK Trf TMS TDI TTsetup TThold TDO TRST* TTRST*low TTDOout TTDOzstate Trf Trf Trf Defined Undefined (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 155 PIC32MX3XX/4XX TABLE 28-41: EJTAG TIMING REQUIREMENTS AC CHARACTERISTICS Param. No. Symbol Description(1) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Max. Units Conditions EJ1 EJ2 EJ3 EJ4 EJ5 EJ6 EJ7 EJ8 EJ9 Note 1: TTCKCYC TTCKHIGH TTCKLOW TTSETUP TTHOLD TTDOOUT TCK Cycle Time TCK High Time TCK Low Time TAP Signals Setup Time Before Rising TCK TAP Signals Hold Time After Rising TCK TDO Output Delay Time From Falling TCK 25 10 10 5 3 -- -- 25 -- -- -- -- -- -- 5 5 -- -- nsec nsec nsec nsec nsec nsec nsec nsec nsec TTDOZSTATE TDO 3-State Delay Time From Falling TCK TTRSTLOW TRF TRST Low Time TAP Signals Rise/Fall Time, All Input and Output These parameters are characterized, but not tested in manufacturing. DS61143F-page 156 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX 29.0 29.1 PACKAGING INFORMATION Package Marking Information 64-Lead TQFP (10x10x1 mm) Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN PIC32MX360F 512L-80I/PT e3 0510017 100-Lead TQFP (12x12x1 mm) Example XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN PIC32MX360F 256L-80I/PT e3 0510017 64-Lead QFN (9x9x0.9 mm) Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN PIC32MX360F 512L-80I/MR e3 0510017 Legend: XX...X Y YY WW NNN * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 157 PIC32MX3XX/4XX 29.2 Package Details [ [ PP %RG\ PP >74)3@ The following sections give the technical details of the packages. /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D D1 E e E1 N b NOTE 1 123 NOTE 2 A c A2 A1 L L1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI /HDGV /HDG 3LWFK 2YHUDOO +HLJKW 0ROGHG 3DFNDJH 7KLFNQHVV 6WDQGRII )RRW /HQJWK )RRWSULQW )RRW $QJOH 2YHUDOO :LGWK 2YHUDOO /HQJWK 0ROGHG 3DFNDJH :LGWK 0ROGHG 3DFNDJH /HQJWK /HDG 7KLFNQHVV /HDG :LGWK 0ROG 'UDIW $QJOH 7RS 0ROG 'UDIW $QJOH %RWWRP 1 H $ $ $ / / I ( ' ( ' F E D E 0,1 0,//,0(7(56 120 %6& 5() %6& %6& %6& %6& 0$; 1RWHV 3LQ YLVXDO LQGH[ IHDWXUH PD\ YDU\ EXW PXVW EH ORFDWHG ZLWKLQ WKH KDWFKHG DUHD &KDPIHUV DW FRUQHUV DUH RSWLRQDO VL]H PD\ YDU\ 'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG PP SHU VLGH 'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( < 0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 5() 5HIHUHQFH 'LPHQVLRQ XVXDOO\ ZLWKRXW WROHUDQFH IRU LQIRUPDWLRQ SXUSRVHV RQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ & % DS61143F-page 158 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 1RWH [ [ PP %RG\ PP >74)3@ )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 159 PIC32MX3XX/4XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS61143F-page 160 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 161 PIC32MX3XX/4XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS61143F-page 162 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 1RWH [ [ PP %RG\ PP >74)3@ )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D D1 e E E1 b N 1 23 NOTE 1 c NOTE 2 A L 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI /HDGV /HDG 3LWFK 2YHUDOO +HLJKW 0ROGHG 3DFNDJH 7KLFNQHVV 6WDQGRII )RRW /HQJWK )RRWSULQW )RRW $QJOH 2YHUDOO :LGWK 2YHUDOO /HQJWK 0ROGHG 3DFNDJH :LGWK 0ROGHG 3DFNDJH /HQJWK /HDG 7KLFNQHVV /HDG :LGWK 0ROG 'UDIW $QJOH 7RS 0ROG 'UDIW $QJOH %RWWRP 1 H $ $ $ / / I ( ' ( ' F E D E 5() %6& %6& %6& %6& %6& 0,1 A1 L1 0,//,0(7(56 120 0$; A2 1RWHV 3LQ YLVXDO LQGH[ IHDWXUH PD\ YDU\ EXW PXVW EH ORFDWHG ZLWKLQ WKH KDWFKHG DUHD &KDPIHUV DW FRUQHUV DUH RSWLRQDO VL]H PD\ YDU\ 'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG 'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( < 0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 5() 5HIHUHQFH 'LPHQVLRQ XVXDOO\ ZLWKRXW WROHUDQFH IRU LQIRUPDWLRQ SXUSRVHV RQO\ PP SHU VLGH 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ & % (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 163 PIC32MX3XX/4XX /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 1RWH [ [ PP %RG\ PP >74)3@ )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ DS61143F-page 164 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX APPENDIX A: REVISION HISTORY Revision E (July 2008) * Updated the PIC32MX340F128H features in Table 1 to include 4 programmable DMA channels. Revision F (June 2009) This revision includes minor typographical and formatting changes throughout the data sheet text. Global changes include: * Changed all instances of OSCI to OSC1 and OSCO to OSC2 * Changed all instances of VDDCORE and VDDCORE/VCAP to VCAP/VDDCORE * Deleted registers in most sections, refer to the related section of the PIC32MX3XX/4XX Family Reference Manual (DS61132). The other changes are referenced by their respective section in the following table. TABLE A-1: MAJOR SECTION UPDATES Update Description Section Name "High-Performance 80 MHz MIPSBased 32-bit Flash Microcontroller 64/100-Pin General Purpose and USB" Added a Packages" column to Table 1 and Table 2. Corrected all pin diagrams to update the following pin names. Previous: Current: PGC!/EMUC1 PGEC1 PGD!/EMUD1 PGED1 PGC2/EMUC2 PGEC2 PGD2/EMUD2 PGED2 Shaded appropriate pins in each diagram to indicate which pins are 5V tolerant. Added 64-Lead QFN package pin diagrams, one for General Purpose and one for USB. Reconstructed Figure 1-1 to include Timers, ADC, and RTCC in the block diagram. Added a new section to the data sheet that provides the following information: * Basic Connection Requirements * Capacitors * Master Clear PIN * ICSP Pins * External Oscillator Pins * Configuration of Analog and Digital Pins * Unused I/Os Updated the memory maps, Figure 4-1 through Figure 4-6. All summary peripheral register maps were relocated to Section 4.0 "Memory Organization". Removed the "Address" column from Table 7-1. Added a second paragraph to Section 12.1.3 "Analog Inputs" to clarify that all pins that share ANx functions are analog by default, because the AD1PCFG register has a default value of 0x0000. Modified bit names and locations in Register 26-5 "DEVID: Device and Revision ID Register". Replaced "TSTARTUP" with "TPU", and "64-ms nominal delay" with "TPWRT", in Section 26.3.1 "On-Chip Regulator and POR". The information that appeared in the Watchdog Timer and the Programming and Diagnostics sections of 61143E version of this data sheet has been incorporated into the Special Features section: Section 26.2 "Watchdog Timer (WDT)" Section 26.4 "Programming and Diagnostics" Section 1.0 "Device Overview" Section 2.0 "Guidelines for Getting Started with 32-bit Microcontrollers" Section 4.0 "Memory Organization" Section 7.0 "Interrupt Controller" Section 12.0 "I/O Ports" Section 26.0 "Special Features" (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 165 PIC32MX3XX/4XX TABLE A-1: MAJOR SECTION UPDATES (CONTINUED) Update Description Section Name Section 28.0 "Electrical Characteristics" In Section 28.1 "DC Characteristics": Added the 64-Lead QFN package to Table 28-3. Updated data in Table 28-5. Updated data in Table 28-7. Updated data in Section 28.2 "AC Characteristics and Timing Parameters", Table 28-4, Table 28-5, Table 28-7 and Table 28-8. Updated data in Table 28-10. Added OS42 parameter to Table 28-17. Replaced Table 28-23. Replaced Table 28-24. Replaced Table 28-25. Updated Table 28-36. Section 29.0 "Packaging Information" Added 64-Lead QFN package marking information to Section 29.1 "Package Marking Information". Added the 64-Lead QFN (MR) package drawing and land pattern to Section 29.2 "Package Details". "Product Identification System" Added the MR package designator for the 64-Lead (9x9x0.9) QFN. DS61143F-page 166 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX INDEX A AC Characteristics 128 Internal RC Accuracy 130 AC Electrical Specifications Parallel Master Port Read Requirements 153 Parallel Master Port Write Requirements 154 Parallel Slave Port Requirements 152 Pinout I/O Descriptions (table) 12 Power-on Reset (POR) and On-Chip Voltage Regulator 109 S Serial Peripheral Interface (SPI) 57, 67, 81, 89, 91, 100 Special Features 101 B Block Diagrams A/D Module 93 Comparator I/O Operating Modes 95 Comparator Voltage Reference 97 Connections for On-Chip Voltage Regulator 109 Input Capture 77 JTAG Compliant Application Showing Daisy-Chaining of Components 110 Output Compare Module 79 Reset System 57 RTCC 91 Type B Timer 19, 65, 75 UART 85 WDT 108 Brown-out Reset (BOR) and On-Chip Voltage Regulator 109 T Timer1 Module 59, 65, 73, 75 Timing Diagrams 10-bit A/D Conversion (CHPS = 01, SIMSAM = 0, ASAM = 0, SSRC = 000) 150 I2Cx Bus Data (Master Mode) 142 I2Cx Bus Data (Slave Mode) 144 I2Cx Bus Start/Stop Bits (Master Mode) 142 I2Cx Bus Start/Stop Bits (Slave Mode) 144 Input Capture (CAPx) 135 OC/PWM 136 Output Compare (OCx) 136 Parallel Master Port Write 153, 154 Parallel Slave Port 152 SPIx Master Mode (CKE = 0) 137 SPIx Master Mode (CKE = 1) 138 SPIx Slave Mode (CKE = 0) 139 SPIx Slave Mode (CKE = 1) 141 Timer1, 2, 3, 4, 5, 6, 7, 8, 9 External Clock 134 Transmission (8-bit or 9-bit Data) 86 UART Reception with Receive Overrun 87 Timing Requirements CLKO and I/O 131 Timing Specifications I2Cx Bus Data Requirements (Master Mode) 142 I2Cx Bus Data Requirements (Slave Mode) 144 Output Compare Requirements 136 Simple OC/PWM Mode Requirements 136 SPIx Master Mode (CKE = 0) Requirements 137 SPIx Master Mode (CKE = 1) Requirements 138 SPIx Slave Mode (CKE = 1) Requirements 141 C Comparator Operation 96 Comparator Voltage Reference Configuring 98 CPU Module 15, 19 D DC Characteristics 120 I/O Pin Input Specifications 124 I/O Pin Output Specifications 125 Idle Current (IIDLE) 122 Operating Current (IDD) 121 Power-Down Current (IPD) 123 Program Memory 125 Temperature and Voltage Specifications 120 V VDDCORE/VCAP Pin 108 Voltage Reference Specifications 126 Voltage Regulator (On-Chip) 108 E Electrical Characteristics 119 AC 128 Errata 10 W Watchdog Timer Operation 108 WWW, On-Line Support 10 F Flash Program Memory 55 RTSP Operation 55 I I/O Ports 71, 85 Parallel I/O (PIO) 72 P Packaging 157 Details 158 Marking 157 PIC32 Family USB Interface Diagram 70 (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 167 PIC32MX3XX/4XX NOTES: DS61143F-page 168 Preliminary (c) 2009 Microchip Technology Inc. PIC32MX3XX/4XX Product Identification System To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC32 MX 3XX F 512 H T - 80 I / PT - XXX Microchip Brand Architecture Product Groups Flash Memory Family Program Memory Size (KB) Pin Count Tape and Reel Flag (if applicable) Speed Temperature Range Package Pattern Flash Memory Family Architecture Product Groups Flash Memory Family MX = 32-bit RISC MCU core 3xx = General purpose microcontroller family 4xx = USB F = Flash program memory = 32K = 64K = 128K = 256K = 512K Examples: PIC32MX320F032H-40I/PT: General purpose PIC32MX, 32 KB program memory, 64-pin, Industrial temp., TQFP package. PIC32MX360F256L-80I/PT: General purpose PIC32MX, 256 KB program memory, 100-pin, Industrial temp., TQFP package. Program Memory Size 32 64 128 256 512 Pin Count H = 64-pin L = 100-pin I = -40C to +85C (Industrial) Temperature Range Package PT = 64-Lead (10x10x1 mm) TQFP (Thin Quad Flatpack) PT = 100-Lead (12x12x1 mm) TQFP (Thin Quad Flatpack) MR = 64-Lead (9x9x0.9 mm) QFN (Plastic Quad Flat) Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise) ES = Engineering Sample Pattern (c) 2009 Microchip Technology Inc. Preliminary DS61143F-page 169 WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 ASIA/PACIFIC Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 ASIA/PACIFIC India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4080 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 03/26/09 DS61143F-page 170 Preliminary (c) 2009 Microchip Technology Inc. |
Price & Availability of PIC32MX4XXF128HT-80IMR
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |